參數(shù)資料
型號(hào)： SiI3124ACBHU
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁數(shù)： 57/88頁
文件大?。?/td> 621K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Silicon Image, Inc.
7.1.12 PCI-X Capability
Address Offset: 40
H
Access Type: Read/Write
Reset Value: 0x0052_5407
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
57
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
M
Reserved
Max Split
E
P
Next Capability Pointer
Capability ID
This register defines the PCI-X Capability. The register bits are defined below.
Bit [31:23]
: Reserved (R) – This bit field is reserved and returns zeros on a read.
Bit [22:20]
: Max Split (R/W) – Maximum Outstanding Split Transactions. This bit field sets the maximum
number of split transactions the device is permitted to have outstanding. This field is initialized to 101
B
to
indicate a maximum of 12 outstanding split transactions possible.
Bit [19:18]
: Max Mem Rd (R/W) – Maximum Memory Read Byte Count. This bit field is initialized to 00
B
.
Bit [17]
: En Rlxd Ord (R/W) – Enable Relaxed Ordering. This bit field defaults to 1 to enable relaxed ordering of
memory transactions.
Bit [16]
: PERR Rcvr (R/W) – Data Parity Recovery Enable. The host driver may set this bit if it can attempt to
recover from data parity errors. If this bit is 0, a System Error will be generated if a data parity error is detected.
Bit [15:08]
: Next Capability Pointer (R) –Next Capability Pointer. This bit field is hardwired to 54
H
to point to the
3
rd
Capabilities register, the MSI Capability.
Bit [07:00]
: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 07
H
to indicate that this is a PCI-X
Capability.
7.1.13 PCI-X Status
Address Offset: 44
H
Access Type: Read/Write/W1C
Reset Value: 0x12C3_FFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
S
R
M
M
M
D
U
S
1
6
Bus Number
Device Number
Function
Number
This register defines the PCI-X capabilities and current operating status of the PCI-X bus. The register bits are defined below.
Bit [31:30]
: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [29]
: Split Comp Err (R/W1C) – Received Split Completion Error Message. This bit is set if a split
completion message is received with the split completion error attribute bit set.
Bit [28:26]
: Max Cum Rd (R) – Designed Maximum Cumulative Read Size. This bit field is hardwired to 100
B
;
this corresponds to a maximum 16K byte cumulative outstanding burst memory read transactions.
Bit [25:23]
: Max Split (R) – Designed Maximum Outstanding Split Transactions. This bit field is hardwired to
101
B
; this corresponds to a maximum of 12 outstanding split transactions.
Bit [22:21]
: Max Rd BC (R) – Designed Maximum Memory Read Byte Count. This bit field is hardwired to 10
B
;
this corresponds to a maximum of 2K bytes for a memory read transaction.
Bit [20]
: DVC Cmplx (R) – Device Complexity. This bit is hardwired to 0; the SiI3124 is not a bridge.
Bit [19]
: UnExp Split (W1C) – Unexpected Split Completion. This bit indicates that an unexpected split
completion was received.
Bit [18]
: Split Discard (W1C) – Split Completion Discarded. This bit indicates that a split completion has been
discarded.
Bit [17]
: 133 MHz (R) – 133 MHz Capable. This bit is hardwired to 1.
Bit [16]
: 64-bit (R) – 64-bit Device. This bit is hardwired to 1.
Bit [15:8]
: Bus Number (R) – This bit field is initialized to FF
H
.
Bit [7:3]
: Device Number (R) – This bit field is initialized to 1F
H
.
Bit [2:0]
: Function Number (R) – This bit field is hardwired to 0
H
.
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