參數(shù)資料
型號(hào)： SiI3124ACBHU
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁(yè)數(shù)： 3/88頁(yè)
文件大?。?/td> 621K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Table of Contents
Silicon Image, Inc.
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
3
1
Overview ...........................................................................................................................................8
1.1
Features ..................................................................................................................................................... 8
1.1.1
1.1.2
1.1.3
1.2
References................................................................................................................................................. 8
Electrical Characteristics ................................................................................................................9
2.1
Device Electrical Characteristics ............................................................................................................ 9
2.2
SATA Interface Timing Specifications.................................................................................................. 11
2.3
SATA Interface Transmitter Output Jitter Characteristics.................................................................. 11
2.4
CLKI SerDes Reference Clock Input Requirements............................................................................ 12
2.5
Power Supply Noise Requirements ...................................................................................................... 12
2.6
PCI 33 MHz Timing Specifications ........................................................................................................ 12
2.7
PCI 66 MHz Timing Specifications ........................................................................................................ 13
2.8
PCI-X 133 MHz Timing Specifications................................................................................................... 13
Pin Definition..................................................................................................................................14
3.1
SiI3124A Pin Listing................................................................................................................................ 14
3.2
SiI3124A Ball Mapping............................................................................................................................ 18
3.3
SiI3124A Pin Descriptions...................................................................................................................... 19
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Package Drawing............................................................................................................................23
Programming Model.......................................................................................................................25
5.1
SiI3124A Block Diagram......................................................................................................................... 25
5.2
SiI3124A S-ATA Port Block Diagram..................................................................................................... 26
5.3
Data Structures ....................................................................................................................................... 27
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.3.10
5.3.11
5.4
Operation ................................................................................................................................................. 39
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
5.4.10
5.4.11
5.4.12
Overall Features...................................................................................................................................................8
PCI-X Features.....................................................................................................................................................8
Serial ATA Features.............................................................................................................................................8
2
3
PCI(X) Pins.........................................................................................................................................................19
Flash / I
2
C Pins...................................................................................................................................................20
Serial ATA Signals..............................................................................................................................................20
Test Pins ............................................................................................................................................................21
NC Pins..............................................................................................................................................................21
Power/Ground Pins ............................................................................................................................................22
4
5
The Command Slot.............................................................................................................................................27
The Scatter/Gather Entry (SGE).........................................................................................................................28
The Scatter/Gather Table (SGT) ........................................................................................................................29
The Port Request Block (PRB)...........................................................................................................................29
The PRB Control Field........................................................................................................................................31
The PRB Protocol Override Field .......................................................................................................................32
Standard ATA Command PRB Structure............................................................................................................33
PACKET Command PRB Structure....................................................................................................................35
Soft Reset PRB Structure...................................................................................................................................36
External Command PRB Structure.....................................................................................................................37
Interlocked Receive PRB Structure....................................................................................................................38
Command Issuance............................................................................................................................................39
Reset and Initialization .......................................................................................................................................39
Port Ready .........................................................................................................................................................40
Port Reset Operation..........................................................................................................................................40
Initialization Sequence........................................................................................................................................40
Interrupts and Command Completion.................................................................................................................41
Interrupt Sources................................................................................................................................................41
Command Completion – The Slot Status Register.............................................................................................44
The Attention Bit.................................................................................................................................................45
Interrupt Service Procedure................................................................................................................................45
Interrupt No Clear on Read ................................................................................................................................45
Error Processing.................................................................................................................................................45
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