參數(shù)資料
型號： SiI3124ACBHU
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁數(shù)： 19/88頁
文件大?。?/td> 621K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Silicon Image, Inc.
3.3 SiI3124 Pin Descriptions
3.3.1 PCI(X) Pins
Signal Name
PCI_AD[63:0]
Data Sheet
2006 Silicon Image, Inc.
SiI-DS-0160-C
19
Pin Number(s)
Description
Address/Attribute/Data.
PCI_AD[63:0] is the multiplexed
address/attribute/data bus. Each bus transaction consists of an address phase
followed by an attribute phase (PCI-X only), then one ore more data phases.
K20, K17, K19, J19,
J20, J17, H20, H17,
H19, G19, G20,
G17, F20, F17, F19,
E19, E20, E17, D20,
D19, C20, C19, B20,
D17, A19, B18, A18,
B17, A17, B16, A16,
D16, Y8, U8, W8,
W9, Y9, U9, Y10,
U10, Y11, U11, Y12,
U12, W12, W13,
Y13, U13, U17, Y18,
W18, V20, V19,
U20, U19, T19, R20,
R17, R19, P19, P20,
P17, N20, N17
PCI_CBEN[7:0]
M19, M20, L19, L20,
W10, Y14, Y17, T17
Command/Byte Enable.
PCI_CBEN is the multiplexed command/byte-enable
bus. During the address phase this bus carries the command. During the
attribute phase (PCI-X only) PCI_CBEN[3:0] carries the upper 4 bits of the byte
count. During the data phase this bus carries byte enables.
Initialization Device Select.
This is the chip select for configuration read/write
operations.
Frame.
PCI_FRAME_N is asserted to indicate the beginning of a bus
operation. It is deasserted when the transaction is in the final data phase or
has completed.
Initiator Ready.
PCI_IRDY_N is asserted by a bus master to indicate that it
can complete a data transaction.
Target Ready.
PCI_TRDY_N is asserted by a target to indicate that it can
complete the current data transaction.
Device Select.
PCI_DEVSEL_N is asserted to indicate that the target has
decoded its own address or a Split Completion cycle (PCI-X only).
Stop.
PCI_STOP_N indicates the current target is requesting that the master
stop the current transaction.
Lock.
PCI_LOCK_N indicates that the current transaction on the PCI bus
needs to be a Locked transaction.
Request.
PCI_REQ_N indicates to the system arbiter that the SiI3124 wants to
gain control of the PCI bus to perform a transaction.
Grant.
PCI_GNT_N indicates that the SiI3124 has been given control of the
bus to perform a transaction.
Request64.
PCI_REQ64_N is asserted by a bus master to request a 64-bit
transaction.
Acknowledge64.
PCI_ACK64_N is asserted by a target to acknowledge that a
64-bit transaction is accepted.
Parity.
PCI_PAR carries even parity covering the PCI_AD[31:0] and
PCI_CBEN[3:0] buses.
Parity.
PCI_PAR64 carries even parity covering the PCI_AD[63:32] and
PCI_CBEN[7:4] buses.
Parity Error.
PCI_PERR_N indicates the detection of a data parity error.
System Error.
PCI_SERR_N indicates detection of an address or attribute
parity error or of any other system error where the result will be catastrophic.
PCI_IDSEL
W11
PCI_FRAME_N
U14
PCI_IRDY_N
W14
PCI_TRDY_N
U16
PCI_DEVSEL_N
W15
PCI_STOP_N
U15
PCI_LOCK_N
Y15
PCI_REQ_N
Y7
PCI_GNT_N
U7
PCI_REQ64_N
M17
PCI_ACK64_N
N19
PCI_PAR
W17
PCI_PAR64
L17
PCI_PERR_N
PCI_SERR_N
W16
Y16
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