參數(shù)資料
型號(hào)： SiI3124ACBHU
廠商： Silicon Image, Inc.
英文描述： PCI-X to Serial ATA Controller
中文描述： PCI - X到串行ATA控制器
文件頁數(shù)： 12/88頁
文件大小： 621K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
2.4 CLKI SerDes Reference Clock Input Requirements
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
12
Limits
Typ
25
100
Symbol
Parameter
Condition
Min
Max
Unit
T
CLKI_FREQ
Nominal Frequency
REXT = 1k 1%
REXT = 4.99k 1%
MHz
V
CLKI_IH
V
CLKI_IL
T
CLKI_J
Input High Voltage
Input Low Voltage
CLKI frequency tolerance
-
-
-
0.7xVDDRX
-50
V
V
0.3xVDDRX
+50
ppm
25MHz reference, 20%-80%
4
T
CLKI_RISE_FALL
Rise and Fall time at CLKI
100MHz reference, 20%-80%
2
ns
T
CLKI_RJ
Random Jitter
Measured at CLKI pin
10
-12
Bit Error Ratio
1 sigma deviation
Measured at CLKI pin
10
Bit Error Ratio
peak-to-peak phase noise
20%-80%
50
psrms
T
CLKI_TJ
Total Jitter
1
ns
T
CLKI_RC_DUTY
CLKI duty cycle
40
60
%
Table 2-7 CLKI SerDes Reference Clock Input Requirements
2.5 Power Supply Noise Requirements
Limits
Typ
Symbol
Parameter
Condition
Min
Max
Unit
V
NOISE_VDDA
1.8V Analog Power Noise
50
mV
V
NOISE_VDDD
1.8V Digital Power Noise
100
mV
V
NOISE_VDDO
3.3V IO Power Noise
peak-to-peak sinewave across
500KHz to 3GHz frequency
range.
Measured with differential probe
trigger by nois source (CLKI and
PCI_CLK)
200
mV
Table 2-8 Power Supply Noise Requirements
2.6 PCI 33 MHz Timing Specifications
Limits
Min
2.0
2.0
2.0
-
7.0
10.0
0.0
Symbol
T
VAL
T
VAL
(PTP)
T
ON
T
OFF
T
SU
T
SU (PTP)
T
H
Parameter
Max
11.0
11.0
-
28.0
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
CLK to Signal Valid – Bussed Signals
CLK to Signal Valid – Point to Point
Float to Active Delay
Active to Float Delay
Input Setup Time – Bussed Signals
Input Setup Time – Point to Point
Input Hold Time
Table 2-9 PCI 33 MHz Timing Specifications
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