參數(shù)資料
型號(hào)： SBPH400-3
廠商： 意法半導(dǎo)體
英文描述： IEEE1394 3-Port 400Mbps Physical Layer
中文描述： IEEE1394連接3端口400Mbps的物理層
文件頁數(shù)： 4/43頁
文件大?。?/td> 285K
代理商： SBPH400-3
4/43
SBPH400-3
1
Overview
The
SBPH400-3
provides the analog transceiver functions needed to implement a 3 port
node in an
IEEE 1394-1995
cable network. There are 2 differential line transceivers in each
cable port. The following main functions are included in the chip:
Detection of connection status using line condition detection circuitry.
Node initialization and bus arbitration.
Reception and Transmission of Data Strobe Bit Level encoded packets
Interface to higher level protocol devices (Link layer).
Production test through JTAG
The interface to the Link conforms to the
IEEE 1394-1995
Annex J with 2 control lines and an
8 bit data bus, as modified by the P1394a proposals.
The basic chip timing may be controlled either from a 24.596 MHz crystal controlling an
internal oscillator or from an external 24.596 MHz oscillator. The internal delay lock loop (DLL)
generates the various internal clocks for the high speed serial data transmission and
reception. Note that there is no need to provide filtering capacitors. The input clock is used to
derive the 49.152 MHz clock for the interface to a Link layer device, which provides the data
to be transmitted on the 8 bit Link data interface. The data from the Link layer device is latched
internally in the chip at 49.152 MHz. The bits are serialized and encoded in the Data Strobe
Bit Level Encoding format. The Data information is transmitted differentially on the
TPB
cable
pair(s) while the Strobe information is transmitted differentially on the
TPA
cable pair(s). Data
can be transmitted at 98.304 Mbit/s (S100 speed), 196.608 Mbit/s (S200 speed) or 393.216
Mbit/sec (S400 speed). When a packet is received by a port, the corresponding transmitters
are disabled and the receivers enabled. The received encoded Data information from
TPA
cable pair and the encoded Strobe information from the
TPB
cable pair are decoded to extract
the receive clock signal and the data bits. The data bits are converted into a parallel format
and transmitted to the Link Layer controller and the other active cable ports after
resynchronisation to the system clock.
Figure 1.1 is a block diagram of the SBPH400-3. The portion of circuit which is circled by the
dash line is termed the
Cable Media Interface
. All signals between the Digital Circuit and the
Cable Media Interface are pure digital signals. The signals which are driven on and received
from the cable are analog differential and common mode signals. The differential signals on
the cable transmit data or arbitration states, while common mode signals indicate the cable
connection status or transmission rate (speed).
2
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