參數(shù)資料
型號(hào)： SBPH400-3
廠商： 意法半導(dǎo)體
英文描述： IEEE1394 3-Port 400Mbps Physical Layer
中文描述： IEEE1394連接3端口400Mbps的物理層
文件頁(yè)數(shù)： 24/43頁(yè)
文件大?。?/td> 285K
代理商： SBPH400-3
24/43
SBPH400-3
2.8.9 Receive
When the SBPH400 detects the “data-on” state on the serial bus, it starts the receive operation
by asserting receive on the CTL pins and ‘1’ on each of the D pins. The SBPH400 indicates
the beginning of the packet by placing on the D pins the speed code, as defined in Table 2.14.
The speed code is followed by the contents of the received packet using the appropriate range
of D pins (D[0:1] for S100, D[0:3] for S200 and D[0:7] for S400). The CTL pins will remain in
the receive state untilthe last symbol of the packet has been transferred to the linkdevice. The
end of the packet is indicated by the CTL pins going back to the idle state. Note that the speed
code is part of the link interface protocol and is not included in the calculation of CRC. Note
that P1394a requires that, for compatibility with 1394-1995 PHYs, if “multi-speed
concatenated packets” is not enabled (see Table 2.16), any concatenated packet which is
received without a speed code is assumed to be transmitted at the same speed as the packet
to which it is concatenated. If the SBPH400 detects such a packet then it will indeed make this
assumption, and will supply the appropriate speed code in front of the packet as it transfers it
to the link device. The receive timing is shown in Figure 2.14.
Figure 2.13
Receive timing
Table 2.14
Speed codes on the LINK-PHY interface
D[0:7]
00000000
01000000
01010000
11111111
Data Rate
S100
S200
S400
“data-on” indication
00
10
10
10
10
10
10
00
00
00
FF
FF
SP
D0
D1
Dn
00
00
CTL[0:1]
D[0:7] (hex)
2
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