參數(shù)資料
型號： SBPH400-3
廠商： 意法半導(dǎo)體
英文描述： IEEE1394 3-Port 400Mbps Physical Layer
中文描述： IEEE1394連接3端口400Mbps的物理層
文件頁數(shù)： 26/43頁
文件大?。?/td> 285K
代理商： SBPH400-3
26/43
SBPH400-3
Power_class
3
R/W
Power class. Set by software to control the value of the pwr field
transmitted in the self-ID packet. On power reset, this is initialized to
the values of the PC[0:2] pins.
Resume interrupt enable. When set to 1, the SBPH400 sets
Port_event to 1 if resume operations commence for any port.
Initialized to 0 on power reset.
Initiate short (arbitrated) bus reset. Unless entry to suspend or resume
is in progress for any of the SBPH400’s ports, a write of one to this bit
requests the SBPH400 to arbitrate after a sub-action gap and issue a
short bus reset. Any outstanding fairrequest is abandoned. Unlike fair
bus requests, the request persists until won, or until a time-out forces
a long bus reset. Always reads as 0.
Loop detect interrupt. Set to one when the Tree-ID process detected
a loop. The PHY_interrupt status bit is set when this bit transitions
from 0 to 1. A register write with the value 1 in the field corresponding
to this bit clears the register to zero. A register write with a value 0 to
the field corresponding to this bit is ignored.
Cable power fail interrupt. Set when the PS register changes from 1 to
0. The PHY_interrupt status bit is set when this bit transitions from 0
to 1. A register write with the value 1 in the field corresponding to this
bit clears the register to zero. A register write with a value 0 to the field
corresponding to this bit is ignored.
State time-out interrupt. Set to 1 when the arbitration state machine
has been in any state other than Idle, Tree-ID state T0, Transmit or
Receive for longer than 300
μ
sec. The PHY_interrupt status bit is set
when this bit transitions from 0 to 1.A register write with the value 1 in
the field corresponding to this bit clears the register to zero. A register
write with a value 0 to the field corresponding to this bit is ignored.
Port event detect. Set to 1 when any of Connected, Bias, Disabled or
Fault change for a port whose Int_enable bit is one, or when resume
operations commence for any port and Resume_int is set to 1. The
PHY_interrupt status bit is set when this bit transitions from 0 to 1. A
register write with the value 1 in the field corresponding to this bit
clears the register to zero. A register write with a value 0 to the field
corresponding to this bit is ignored.
Enable ACK accelerated and fly-by arbitration. Initialized to 0 on
power reset.
Enable multi-speed packet concatenation. Initialized to 0 on power-on
reset.
Resume_int
1
R/W
ISBR
1
R/W
Loop
1
R/W
Pwr_fail
1
R/W
State t_out
1
R/W
Port_event
1
R/W
Enab_accel
1
R/W
Enab_multi
1
R/W
Table 2.16
SBPH400 register fields (continued)
Field
Size
Type
Description
2
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