參數(shù)資料
型號(hào)： SBPH400-3
廠商： 意法半導(dǎo)體
英文描述： IEEE1394 3-Port 400Mbps Physical Layer
中文描述： IEEE1394連接3端口400Mbps的物理層
文件頁(yè)數(shù)： 29/43頁(yè)
文件大小： 285K
代理商： SBPH400-3
SBPH400-3
29/43
On Power on, the Reset# pin should be held low for 2ms to allow supplies to settle. To reset
the device when V
DD
is already present, the Reset# pin should be held low until a minimum of
100ns after the external oscillator (if used) is started and operating within specification. The
SBPH400 willwait for approximately 500
μ
secto allow its internal clocking circuitry to stabilize.
At the end of the nominal 500
μ
sec period, the SBPH400 becomes fully operational. Prior to
the SBPH400 becoming fully operational, all outputs on the PHY/Link interface are held in high
impedance, as are the TpBias and TPA and TPB pins for all three ports. When the SBPH400
becomes fullyoperational, it senses the ISO, PC[0:2], CMC, LACT and PDISABLE. If ISO = 0,
then all outputs on the PHY/Link interface are taken to zero, and the SBPH400 will also then
respond to LPS if this pin is active (see 2.9.2).
2.9.2 PHY/Link Interface start-up
The PHY/Link interface is controlled by the link device via the LPS signal. In order to indicate
to the SBPH400 that the linkinterface is active, LPS should either beheld to a logic 1 (possibly
by connecting to the V
DD
supplying the link layer device) or be connected to a pulsed output
which meets the specification shown in Figure 2.15 and Table 2.20. If neither of these is true
after power reset (see above), then no signal is considered to be received on LPS, the link
interface continues to be disabled, and the SBPH400 operates as a PHY repeater.
Figure 2.15
LPS timing (isolated interface)
When LPS is asserted, the PHY/Link interface starts as illustrated in Figure 2.16
Table 2.20
LPS timings
Symbol
T
LPSL
T
LPSH
Parameter
LPS low time (isolated interface)
LPS high time (Isolated interface)
Unit
ns
ns
Min
90
90
Typ
Max
1000
1000
T
LPSH
T
LPSL
LPS
(isolated)
2
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