參數(shù)資料
型號(hào)： SBPH400-3
廠商： 意法半導(dǎo)體
英文描述： IEEE1394 3-Port 400Mbps Physical Layer
中文描述： IEEE1394連接3端口400Mbps的物理層
文件頁(yè)數(shù)： 25/43頁(yè)
文件大?。?/td> 285K
代理商： SBPH400-3
SBPH400-3
25/43
2.8.10 SBPH400 registers
The accessible SBPH400 registers are listed in Table 2.15. The descriptions of the fields are
given in Table 2.16.
Table 2.15
Accessible SBPH400 register
Address
0000
0001
0010
0011
0100
0101
0
1
2
3
4
5
6
R
7
Physical_ID
PS
RHB
IBR
Gap_count
111b (Extended)
Max speed
C
ISBR
rsv
rsv
0011b (Total ports)
0000b (Delay)
Power_class
Port
event
Link_active
Resume_
int
000b (Jitter)
Pwr-fail
Loop
State
t_out
Enab_
accel
Enab_
multi
0110
0111
rsv
Page_select
rsv
Port_select
1000-1111
Register 0-7 [Page_select]
Table 2.16
SBPH400 register fields
Field
Physical_ID
R
PS
Size
6
1
1
Type
R
R
R
Description
The address of the node determined during self-identification.
When set to 1, indicates that the node is the root.
Cable power status. This value always reflects the filtered voltage
sensed on the CPS pin.
Root Hold-off bit. When set to 1, instructs the node to attempt to
become the root during the next Tree-ID process. Value on power
reset is 0.
Initiate Bus Reset bit. When set to 1, instructs the SBPH400 to initiate
a bus reset for 166
μ
sec immediately. Always reads as zero.
Arbitration timer setting. Used to optimize gap times based on the
topology of the network.
Always reads as 111b to indicate use of the extended PHY register
map
Always reads as 3
010b (maximum speed is S400)
0000b (maximum repeater delay is 144 ns)
Set or cleared by software. Note that the value of the L bit transmitted
in the self-ID packet is the AND of the Link_active bit and the LPS pin.
Initialized to the value of the LACT configuration pin on power reset.
Contender. Set or cleared by software to control the value of the C bit
transmitted in the self-ID packet. On power reset this is initialized to
the value of the CMC pin.
000b (fastest and slowest repeater delay differ by 20ns)
RHB
1
R/W
IBR
1
R/W
Gap_Count
6
R/W
Extended
3
R
Total_Ports
Max_Speed
Delay
Link_active
4
3
4
1
R
R
R
R/W
C
1
R/W
Jitter
3
R
2
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