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參數(shù)資料
| 型號(hào)： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴(kuò)展的PCM接口控制器？ |
| 文件頁數(shù)： | 44/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
44
PT0105(08/02)
Ver:0
Interrupt Status Register (ISTA) Address: 1CH(0/EH) Read
Value after reset: 00000000B
7 0
TIN
SFI
MFFI
MAC
PFI
PIM
SIN
SOV
The ISTA register should be read after an interrupt in order to determine the interrupt source.
TIN
Timer interrupt;
a timer interrupt previously requested with CMDR: ST,TIG = 1 has occurred. The TIN bit is reset
by reading ISTA. It should be noted that the interrupt generation is periodic, i.e. unless stopped by writing to TIMR, the
ISTA:TIN will be generated each time the timer expires.
SFI
Signaling FIFO Interrupt;
this interrupt is generated if there is at least one valid entry in the CIFIFO indicating
a change in a C/I or SIG channel. Reading ISTA does not clear the SFI bit. Instead SFI is cleared if the CIFIFO is empty
which can be accomplished by reading all valid entries of the CIFIFO or by resetting the CIFIFO by setting CMDR:
CFR to 1.
MFFI
MFFIFO Interrupt;
the last MF-channel command (issued by CMDR: MFT1, MFT0) has been executed and the
PT7D6555 is ready to accept the next command. Additional information can be read from STAR: MFTO
…
MFFE.
MFFI is reset by reading ISTA.
MAC
Monitor channel Active interrupt
; the PT7D6555 has found an active monitor channel. A new search can be started
by reissuing the CMDR: MFSO command. MAC is reset by reading ISTA.
PFI
PCM Framing Interrupt;
the STAR:PSS bit has changed its polarity. To determine whether the PCM-interface is
synchronized or not, STAR must be read. The PFI bit is reset by reading ISTA.
PIM
PCM Input Mismatch;
this interrupt is generated immediately after the comparison logic has detected a mismatch
between a pair of PCM input lines. The exact reason for the interrupt can be determined by reading the PICM register.
Reading ISTA clears the PIM-bit. A new PIM interrupt can only be generated after the PICM register has been read.
SIN
Synchronous transfer Interrupt;
The SIN interrupt is enabled if at least one synchronous transfer channel (A and/
or B) is enabled via the STCR: TAE, TBE bits. The SIN interrupt is generated when the access window for the mP opens.
After the occurrence of the SIN interrupt the mP can read and/or write the synchronous transfer data registers (STDA,
STDB). The SIN bit is reset by reading ISTA.
SOV
Synchronous transfer Overflow;
The SOV interrupt is generated if the
μ
P fails to access the data registers (STDA,
STDB) within the access window. The SOV bit is reset by reading ISTA.
Mask Register (MASK) Address: 1CH(0/EH) Write
Value after reset: 00000000B
7 0
TIN
SFI
MFFI
MAC
PFI
PIM
SIN
SOV
A logical 1 disables the corresponding interrupt as described in the ISTA-register. A masked interrupt is stored internally and
reported in ISTA immediately if the mask is released. However, an SFI interrupt is also reported in ISTA if masked. In this case
no interrupt is generated. When writing register MASK while ISTA indicates a non masked interrupt INT is temporarily set into
the inactive state.
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