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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
30
PT0105(08/02)
Ver:0
Configurable Interface Mode Register 2 (CMD2)
Value after reset: 00000000B
Address: 2EH(1/7H)
Read/Write
7 0
FC2
FC1
FC0
COC
CXF
CRR
CBN9
CBN8
FC2..0
Framing output Control.
Given that CMD1: CSS = 0, these bits determine the position of the FSC pulse relative to the CFI frame, as well as the
type of FSC pulse generated. The position and width of the FSC signal with respect to the CFI frame can be found in
the following two figures 14 and 15.
Table 3 The FSC signal Application
FSC2
FSC1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FSC0
0
1
0
1
0
1
0
1
FS-Mode
0
1
2
3
4
5
6
7
Main Application
IOM-1 multiplexed (burst) mode
general purpose
general purpose
general purpose
2 ISAC-S per SLD-port
reserved
IOM-2 or SLD modes
software timed multiplexed applications
COC
CFI Output Clock rate.
0
…
the frequency of DCL is identical to the CFI data rate (all CFI modes),
1
…
the frequency of DCL is twice the CFI data rate (CFI modes 0 and 3 only!)
Note
: Applies only if CMD1: CSS = 0.
CXF
CFI Transmit on Falling edge.
0
…
the data is transmitted with the rising CRCL edge,
1
…
the data is transmitted with the falling CRCL edge.
CRR
CFI Receive on Rising edge.
0
…
the data is received with the falling CRCL edge,
1
…
the data is received with the rising CRCL edge.
Note:
CRR must be set to 0 in CFI-mode 3.
CBN9, 8
CFI Bit Number 9, 8
These bits, together with the CBNR: CBN7..0, hold the number of bits per CFI frame.
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