參數(shù)資料
型號(hào)： PT7D6555
英文描述： -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package
中文描述： 擴(kuò)展的PCM接口控制器？
文件頁(yè)數(shù)： 35/56頁(yè)
文件大?。?/td> 489K
代理商： PT7D6555
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
35
PT0105(08/02)
Ver:0
3) Writing data to the upstream or downstream CM data field (e.g. signaling code). Reading data from the upstream or down-
stream CM data field.
MACR:
RWS
1
0
0
1
0
0
0
4) Writing data to the upstream or downstream CM data and code field (e.g. switching a CFI to/from PCM connection).
MACR:
0
1
1
1
CMC3 CMC2 CMC1 CMC0
The 4-bit code field of the control memory (CM) defines the functionality of a CFI time slot and thus the meaning of the
corresponding data field. This 4-bit code, written to the MACR: CMC3..0 bit positions, will be transferred to the CM code field.
The 8-bit MADR value is at the same time transferred to the CM data field. There are codes for switching applications, pre-
processed applications and for direct mP access applications, as shown below:
a) Switching Applications
CMC = 0000 Unassigned channel (e.g. canceling an assigned channel)
CMC = 0001 Bandwidth 64 kbit/s PCM time slot bits transferred: 7
…
0
CMC = 0010 Bandwidth 32 kbit/s PCM time slot bits transferred: 3
…
0
CMC = 0011 Bandwidth 32 kbit/s PCM time slot bits transferred: 7
…
4
CMC = 0100 Bandwidth 16 kbit/s PCM time slot bits transferred: 1
…
0
CMC = 0101 Bandwidth 16 kbit/s PCM time slot bits transferred: 3
…
2
CMC = 0110 Bandwidth 16 kbit/s PCM time slot bits transferred: 5
…
4
CMC = 0111 Bandwidth 16 kbit/s PCM time slot bits transferred: 7
…
6
Note: The corresponding CFI time slot bits to be transferred are chosen in the CSCR-register.
b) Pre-processed Applications
Downstream:
Application
Decentral D channel handling
Central D channel handling
6-bit Signaling (e.g. analog IOM)
8-bit Signaling (e.g. SLD)
Even CM Address
CMC = 1000
CMC = 1010
CMC = 1010
CMC = 1010
Odd CM Address
CMC = 1011
CMC = PCM code for a 2-bit subtime slot
CMC = 1011
CMC = 1011
Upstream:
Application
Decentral D channel handling
Central D channel handing
6-bit Signaling (e.g. analog IOM)
8-bit Signaling (e.g. SLD)
Even CM Address
CMC = 1000
CMC = 1000
CMC = 1010
CMC = 1011
Odd CM Address
CMC = 0000
CMC = PCM code for a 2-bit subtime slot
CMC = 1010
CMC = 1011
c)
μ
P-access Applications
MACR:
0
1
1
1
1
0
0
1
Setting CMC = 1001, initializes the corresponding CFI time slot to be accessed by the mP. Concurrently, the datum in MADR
is written (as 8-bit CFI-idle code) to the CM data field. The content of the CM data field is directly exchanged with the
corresponding time slot.
Note:
Once the CM code field has been initialized, the CM data field can be written and read as described in subsection 3.
5) Control-reading the upstream or downstream CM code.
MACR:
1
1
1
1
The CM code can then be read out of the 4 LSBs of the MADR register.
0
0
0
0
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