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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 24/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
24
PT0105(08/02)
Ver:0
Example
In CFI-mode 0 all four CFI-ports shall be initialized as IOM-2
ports with a 4-bit C/I-field and decentral D channel handling.
CFI time slots 0, 1, 4, 5, 8, 9
…
28, 29 of each port are B
channels and need not to be initialized. CFI time slots 2, 3, 6,
7, 10, 11
…
30, 31 of each port are pre-processed channels and
need to be initialized:
CFI-port 0, time slot 2 (even), downstream
MADR = FFH; the C/I-value
“
1111
”
will be transmitted upon
CFI activation
MAAR = 08H; addresses ts 2 down
MACR = 78H; CM-code
“
1000
”
Wait for STAR: MAC = 0
CFI-port 0, time slot 3 (odd), downstream
MADR = FFH; don
’
t care
MAAR = 09H; addresses ts 3 down
MACR = 7BH; CM-code
“
1011
”
Wait for STAR: MAC = 0
CFI-port 0, time slot 2 (even), upstream
MADR = FFH; the C/I-value
“
1111
”
is expected upon CFI
activation
MAAR = 88H; address ts 2 up
MACR = 78H; CM-code
“
1000
”
Wait for STAR: MAC = 0
CFI-port 0, time slot 3 (odd), upstream
MADR = FFH; don
’
t care
MAAR = 89H; address ts 3 up
MACR = 70H; CM-code
“
0000
”
Wait for STAR: MAC = 0
Repeat the above programming steps for the remaining CFI
ports and time slots. This procedure can be speeded up by
selecting the CM initialization mode (OMDR: OMS1, 0 = 10).
If this selection is made, the access time to a single memory
location is reduced to 2.5 RCL cycles. The complete initial-
ization time for 32 IOM-2 channels is then reduced to 128 x
0.61
μ
s = 78
μ
s.
Initialization of the Upstream Data Memory (DM) Tristate
Field
For each PCM time slot the tristate field defines whether the
contents of the DM data field are to be transmitted (low imped-
ance), or whether the PCM time slot shall be set to high imped-
ance. The contents of the tristate field are not modified by a
hardware reset. In order to have all PCM time slots set to high
impedance upon the activation of the PCM-interface, each
location of the tristate field must be loaded with the value
’
0000
’
. For this purpose, the
‘
tristate reset
’
command can be
used:
OMDR = C0H; OMS1, 0 = 11, normal mode
MADR = 00H; code field value
“
0000
”
B
MACR = 68H; MOC-code to initialize all tristate locations
(1101B)
Wait for STAR: MAC = 0
The initialization of the complete tristate field takes 1035
RCL cycles.
Notes:
1.
It is also possible to program the value
“
0000
”
to the tristate
field in order to have all time slots switched to low impedance
upon the activation of the PCM interface.
2.
While OMDR: PSB = 0, all PCM-output drivers are set to
high impedance, regardless of the values written to the tristate
field.
Activation of the PCM and CFI Interfaces
With the PT7D6555 configured to the system requirements,
the PCM and CFI interface can be switched to the operational
mode.
The OMDR: OMS1..0 bits must be set (if this has not already
been done) to the normal operation mode (OMS1, 0 = 11).
When doing this, the PCM framing interrupt (ISTA: PFI) will
be enabled. If the applied clock and framing signals are in
accordance with the values programmed to the PCM-registers,
the PFI interrupt will be generated (if not masked). When read-
ing the status register, the STAR: PSS-bit will be set to logical
1.
To enable the PCM-output drivers set OMDR: PSB = 1. The
CFI interface is activated by programming OMDR: CSB = 1.
This enables the output clock and framing signals (DCL and
FSC), if these have been programmed as outputs. It also en-
ables the CFI output drivers. The output driver type can be
selected between
“
open drain
”
and
“
tristate
”
with the OMDR:
COS bit.
Example: Activation of the PT7D6555 for a typical IOM-2
application:
OMDR = EEH; Normal operation mode (OMS1, 0 = 11)
PCM interface active (PSB = 1)
PCM test loop disabled (PTL = 0)
CFI output drivers: open drain (COS = 1)
Monitor handshake protocol selected (MFPS = 1)
CFI active (CSB = 1)
Access to PT7D6555 registers via address pins A3
…
A0, used
in demultiplexed mode only, normal operation (RBS = 0)
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