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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 34/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
34
PT0105(08/02)
Ver:0
Memory Access Registers
Memory Access Control Register (MACR)
Value after reset: XXXXXXXXB
7 0
RWS
MOC3 MOC2 MOC1 MOC0 / CMC3 CMC2 CMC1 CMC0
Address: 00H(0/0H)
Read/Write
With the MACR the mP selects the type of memory (CM or DM), the type of field (data or code) and the access mode (read or
write) of the register access. When writing to the control memory code field, MACR also contains the 4 bit code (CMC3...0)
defining the function of the addressed CFI time slot.
RWS
Read/Write Select.
0
…
write operation on control or data memories
1
…
read operation on control or data memories
MOC3..0
Memory Operation Code.
CMC3..0
Control Memory Code.
These bits determine the type and destination of the memory operation as shown below.
Note: Prior to a new access to any memory location (i.e. writing to MACR) the STAR: MAC bit must be polled for
“
0
”
.
1) Writing data to the upstream DM data field (e.g. PCM idle code). Reading data from the upstream or downstream DM data
field.
MACR:
RWS
MOC3 MOC2 MOC1 MOC0 0
0
0
MOC3..0
defines the bandwidth and the position of the subchannel as shown below:
MOC3… 0
0000
0001
0011
0010
0111
0110
0101
0100
Transferred Bits
-
Bits 7
…
0
Bits 7
…
4
Bits 3
…
0
Bits 7
…
6
Bits 5
…
4
Bits 3
…
2
Bits 1
…
0
Channel Bandwidth
-
64 kbit/s
32 kbit/s
32 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
16 kbit/s
Note: When reading a DM data field location, all 8 bits are read regardless of the bandwidth selected by the MOC bits.
2) Writing to the upstream DM code (tristate) field. Control-reading the upstream DM code (tristate).
MACR:
RWS
MOC3 MOC2 MOC1 MOC0 0
0
0
MOC = 1100
MOC = 1101
Read/write tristate info from/to single PCM time slot
Write tristate info to all PCM time slots
Note:
The tristate field is exchanged with the 4 least significant bits (LSBs) of the MADR.
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