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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 23/56頁 |
| 文件大小： | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
23
PT0105(08/02)
Ver:0
Initialization Procedure
For proper initialization of the PT7D6555 the following pro-
cedure is recommended:
Hardware Reset
A reset pulse can be applied at the RES pin for at least 4 PDC
clock cycles. The reset pulse sets all registers to their reset
values (refer to chapter
Address Assignment
).
Note:
In this state DCL and FSC do not provide any clock
signals.
PT7D6555 Initialization
Register Initialization
The PCM and CFI configuration registers (PMOD, PBNR
…
CMD1, CMD2
…
) have to be programmed to the values re-
quired for the application. The correct setting of the PCM and
CFI registers is important in order to obtain a reference clock
(RCL) which is consistent with the externally applied clock
signals.
The state of the operation mode (OMDR: OMS1, 0 bits) does
not matter for this programming step.
PMOD = PCM-mode, timing characteristics, etc.
PBNR = Number of bits per PCM-frame
POFD = PCM-offset downstream
POFU = PCM-offset upstream
PCSR = PCM-timing
CMD1 = CFI-mode 1
CMD2 = CFI-mode 2
CBNR = Number of bits per CFI-frame
CTAR = CFI-offset (time slots)
CBSR = CFI-offset (bits)
CSCR = CFI-sub channel positions
Control Memory Reset
Since the hardware reset does not affect the PT7D6555 memo-
ries (Control and Data Memories), it is mandatory to perform a
“
software reset
”
of the CM. The CM code
“
0000
”
B (unas-
signed channel) should be written to each location of the CM.
The data written to the CM data field is then don
’
t care, e.g.
FFH.
OMDR: OMS1, 0 must be to
“
00
”
B for this procedure (reset
value).
MADR = FF H
MACR = 70 H
Wait for STAR:MAC =
“
0
”
The resetting of the complete CM takes 256 RCL clock cycles.
During this time, the STAR:MAC-bit is set to logical
“
1
”
.
Initialization of Pre-processed Channels
After the CM reset, all CFI time slots are unassigned. If the CFI
is used as a plain PCM interface, i.e. containing only switched
channels (B channels), the initialization steps below are not
required. The initialization of pre-processed channels applies
only to IOM or SLD applications.
An IOM or SLD
“
channel
”
consists of four consecutive time
slots. The first two time slots, the B channels need not be
initialized since they are already set to unassigned channels
by the CM reset command. Later, in the application phase of
the software, the B channels can be dynamically switched ac-
cording to system requirements. The last two time slots of such
an IOM or SLD channel, the pre-processed channels must be
initialized for the desired functionality. There are four options
that can be selected. See Table 2.
Table 2. Pre-processed Channel Options at the CFI
Even CFI Time Slot
Monitor/feature control channel
Odd CFI Time Slot
4-bit C/I channel, D channel not
switched (decentral D channel
handling)
Main Application
IOM-1 or IOM-2
digital subscriber
Monitor/feature control channel
4-bit C/I channel, D channel switched
(central D channel handling)
IOM-1 or IOM-2
digital subscriber
Monitor/feature control channel
6-bit SIG channel
IOM-2
analog subscriber
SLD
analog subscriber
Monitor/feature control channel
8-bit SIG/channel
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