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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
16
PT0105(08/02)
Ver:0
Pre-processed Channels, Layer-1 Support
The PT7D6555 supports the monitor/feature control and con-
trol/signalling channels according to SLD or IOM-2 interface
protocol.
The monitor handler controls the data flow on the monitor/
feature control channel either with or without an active hand-
shake protocol. To reduce the dynamic load of the CPU a 16-
byte transmit/receive FIFO is provided.
The signaling handler supports different schemes (D-channel
+ C/I-channel, 6-bit signaling, 8-bit signaling). In downstream
direction the relevant content of the control memory is trans-
mitted in the appropriate CFI time slot. In the case of central-
ized ISDN D-channel handling, a 16-kbit/s D-channel received
at the PCM-interface is included. In upstream direction the
signaling handler monitors the received data. Upon a change
it generates an interrupt, the channel address is stored in the 9-
byte deep C/I FIFO and the actual value is stored in the control
memory. In 6-bit and 8-bit signaling schemes a double last
look check is provided.
Special Functions
Synchronous transfer
This utility allows the synchronous
μ
P-access to two indepen-
dent channels on the PCM or CFI interface. Interrupts are gen-
erated to indicate the appropriate access windows.
7-bit hardware timer
The timer can be used to cyclically interrupt the CPU, to deter-
mine the double last look period, to generate a proper CFI-
multiframe synchronization signal or to generate a defined
RESIN pulse width.
Frame length checking
The PFS period is internally checked against the programmed
frame length.
Alternative input functions
In PCM mode 1 and 2, the unused ports can be used for redun-
dancy purposes. In these modes, for every active input port a
second input port exists which can be connected to a redun-
dant PCM line. Additionally the two lines are checked for
mismatches.