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參數(shù)資料
| 型號： | PT7D6555 |
| 英文描述： | -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package |
| 中文描述： | 擴展的PCM接口控制器？ |
| 文件頁數(shù)： | 14/56頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PT7D6555 |
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
14
PT0105(08/02)
Ver:0
Functional Description
Bus Interface
All registers and the FIFOs of the PT7D6555 are accessible via
the flexible bus interface supporting Intel and Motorola type
microprocessors. Depending on the register functionality a
read, write or read/write access is possible.
The bus interface consists of the following elements
·
Data bus, 8-bit wide, D7 - D0
·
Address bus, 4-bit wide, A3 - A0
·
Chip select, CS
·
Address latch enable, ALE
·
Two read/write control lines: RD and WR (Intel mode) or
DS and R/W (Motorola mode)
·
Interrupt, INT
·
Reset, RES
The ALE line is used to control the bus structure and interface
type. See Table 1.
In order to simplify the use of 8- and 16-bit Intel type CPUs,
different register addresses are defined in multiplexed and
demultiplexed bus mode. In the multiplexed mode even ad-
dresses are used (AD0 always 0).
For a demultiplexed
μ
P interface mode the OMDR: RBS bit is
needed in addition to the address lines A3 - A0. With OMDR:
RBS (register bank selection) one of two register banks is se-
lected.
RBS =
“
1
”
selects a set of registers used for device initializa-
tion (e.g. CFI and PCM interface initialization).
RBS =
“
0
”
switches to a group of registers necessary during
operation (e.g. connection programming).
The OMDR register containing the RBS bit can be accessed
with either value of RBS.
Interrupts
An interrupt of the PT7D6555 is indicated by activating the
INT line. The detailed cause of the request can be determined
by reading the ISTA register.
The INT output is level active. It remains active until all inter-
rupt sources have been serviced. If a new status bit is set while
an interrupt is being serviced, the INT remains active. When
using an edge-triggered interrupt controller, it is thus recom-
mended to rewrite the MASK register at the end of any inter-
rupt service routine.
Every interrupt source can be selectively masked by setting
the respective bit of the MASK register. Such masked inter-
rupts will not be indicated in the ISTA register, nor will they
activate the INT line.
PCM Interface
The PCM interface formats the data transmitted or received at
the PCM highways. It can be configured to provide one (max.
8.192 Mbit/s), two (max. 4.096 Mbit/s) or four (max. 2.048
Mbit/s) PCM-ports, consisting each of a data receive (RXD), a
data transmit (TXD) and an output tristate indication line (TSC).
The PCM interface is supplied with a frame signal (PFS) and a
PCM clock (PDC). To properly clock the PCM interface, a
PDC signal with a frequency equal or twice the data rate has to
be applied to the PT7D6555.
Port configuration, data rates, clock shift and sampling condi-
tions are programmable.
Configurable Interface
In order to optimize the on-board interchip communication, a
very flexible serial interface is available. It formats the data
transmitted or received at the DDn-, DUn- or SIPn-lines. Al-
though it is typically used in IOM-2 or SLD-configuration to
connect layer-1 devices, application specific frame structures
can be defined (e.g. to interface ADPCM-converters or mainte-
nance blocks). Figure 10 shows the IOM-2 interface structure
in Line Card Mode.
Table 1. Selectable Bus Configurations
ALE
Interface
Bus Structure
Pin 28
Pin 29
Fixed to Vcc
Motorola
demultiplexed
DS
R/W
Fixed to GND
Intel
demultiplexed
RD
WR
Switching
Intel
multiplexed
RD
WR
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