參數(shù)資料
型號： PT7D6555
英文描述： -40V Single P-Channel HEXFET Power MOSFET in a TSOP-6 (Micro 6) package
中文描述： 擴展的PCM接口控制器？
文件頁數(shù)： 36/56頁
文件大小： 489K
代理商： PT7D6555
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Preliminary Data Sheet
PT7D6555
Extended PCM Interface Controller
36
PT0105(08/02)
Ver:0
Memory Access Address Register (MAAR)
Value after reset: XXXXXXXXB
Address: 02H(0/1H)
Read/Write
7 0
U/D
MA6
MA5
MA4
MA3
MA2
MA1
MA0
The Memory Access Address Register MAAR specifies the address of the memory access. This address encodes a CFI time slot
for control memory (CM) and a PCM time slot for data memory (DM) accesses. Bit 7 of MAAR (U/D bit) selects between
upstream and downstream memory blocks. Bits MA6..0 encode the CFI or PCM port and time slot number as in the following
tables:
Table 4 Time Slot Encoding for Data Memory Accesses
PCM-mode 0
bit U/D
bits MA6..MA3, MA0
bits MA2..MA1
bit U/D
bits MA6..MA3, MA1, MA0
bit MA2
bit U/D
bits MA6..MA0
Direction selection
Time slot selection
Logical PCM port number
Direction selection
Time slot selection
Logical PCM port number
Direction selection
Time slot selection
PCM-mode 1,3
PCM-mode 2
Table 5 Time Slot Encoding for Control Memory Accesses
CFI – mode 0
bit U/D
bits MA6..MA3, MA0
bits MA2..MA1
bit U/D
bits MA6..MA3, MA2, MA0
bit MA1
bit U/D
bits MA6..MA0
bit U/D
bits MA6..MA4, MA0
bits MA3..MA1
Direction selection
Time slot selection
Logical CFI port number
Direction selection
Time slot selection
Logical CFI port number
Direction selection
Time slot selection
Direction selection
Time slot selection
Logical CFI port number
CFI – mode 1
CFI – mode 2
CFI – mode 2
Memory Access Data Register (MADR)
Value after reset: XXXXXXXXB
Address: 04H(0/2H)
Read/Write
7 0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
The Memory Access Data Register MADR contains the data to be transferred from or to a memory location. The meaning and the
structure of this data depend on the kind of memory being accessed.
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