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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
30
Pin Name
Type
Pin
No.
Function
RAM1_ADSCB
/RAM1_R/WB
Output
B21
This signal has different meanings depending
upon the type of SSRAM that the AAL1gator-32
is programmed to interface to.
Pipelined Single-Cycle Deselect SSRAM
:
RAM1 Address Status Control is an active low
output for external memory and is used to
cause a new external address to be loaded into
the RAM.
Pipelined ZBT SSRAM
: RAM1 R/W indicates
the direction of the transfer.
Maximum output current (IMAX) = 6 mA.
RAM1_PAR[1]
RAM1_PAR[0]
I/O
C16
B17
RAM1 Parity is a two bit bi-directional signal that
indicates odd parity for the upper and lower byte
of RAM1_D[15:0].
Maximum output current (IMAX) = 6 mA
Note:
For different modes of the line interface the I/O is redefined. For Direct
Low Speed mode there are 16 pairs of bi-directional lines, which can support
links up to 2.5 Mbps. For H-MVIP mode there are eight pairs of 8 Mbps
bidirectional lines, which are compatible with the H-MVIP specification. For High
Speed mode there are two lines, which can support unchannelized data streams
up to 45 Mbps. And lastly, there is the SBI mode, which supports one SBI
interface. For H-MVIP mode, high speed (HS) mode and SBI mode the upper 8
Direct Low Speed lines become the 2
nd
ram interface. For SBI mode the bottom
8 Direct Low Speed lines become the SBI interface.
Table 1 defines which signal tables need to be used for each possible mode.
Select the mode of the line interface that will be used and refer to the tables
listed. Table 2 on page 48 shows how pins are shared between the different
modes.
Table 1 Line Interface Signal Table Selection
Line Mode
Line Interface Table
RAM2 Interface Table
Direct Low Speed
Direct Low Speed
No
H-MVIP
H-MVIP
Yes (if using upper 4 lines)
SBI
SBI
Yes