![](http://datasheet.mmic.net.cn/330000/PM73122_datasheet_16444367/PM73122_41.png)
RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
9
PIN DIAGRAM
The AAL1gator-32 is manufactured in a 352 pin enhanced ball grid array (SBGA)
package.
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
vss5
vss4
TMS
TDO
RAM1_AD
PCH
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RL_CLK
TL_CLK
vss3
vss2
RAM1_D
RAM1_D
PCH
TL_DATA
RAM1_OE
RAM1_D
RAM1_D
TL_SYNC
TL_SYNC
RL_SIG [7]
vss1
vss0
A
B
vss9
vdd10
vss8
SYS_CLK
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_PA
RAM1_W
RL_CLK
RAM1_D
RAM1_D
RAM1_D
RL_SYNC
TL_SYNC
RAM1_D
RAM1_D
CRL_CLK
RL_DATA
LINE_MO
TL_DATA
vss7
vdd9
vss6
B
C
TATM_DA
vss11
vdd12
TDI
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_CS
RAM1_AD
RAM1_AD
RAM1_PA
TL_CLK
RAM1_D
RAM1_D
SCAN_EN
RL_DATA
RAM1_D
RAM1_D
CTL_CLK
RL_SYNC
TL_DATA
TL_SIG [7]
RL_SYNC
vdd11
vss10
TL_CLK
C
D
TATM_DA
TATM_DA
TATM_DA
vdd17
TCLK
RAM1_AD
RAM1_AD
RAM1_AD
vdd16
RAM1_AD
RAM1_W
RAM1_D
vdd15
RAM1_D
RL_SIG [8]
TL_SIG [8]
RAM1_D
vdd14
RL_SIG [9]
TL_SIG [9]
TL_CLK
RL_CLK
vdd13
RL_DATA
TL_SIG [6]
RL_CLK
D
E
TATM_PA
TATM_DA
RPHY_AD
TATM_DA
TL_SYNC
TL_DATA
RL_SYNC
TL_CLK
E
F
TATM_CL
RPHY_AD
TATM_DA
TATM_DA
RL_SIG [6]
RL_DATA
TL_SIG [5]
RL_CLK
F
G
TATM_SO
RPHY_AD
RPHY_AD
PCH
TL_SYNC
TL_DATA
RL_SYNC
TL_SYNC
G
H
TL_CLK
RL_CLK
TATM_EN
RPHY_AD
RL_SIG [5]
RL_DATA
TL_CLK
RL_SIG [4]
H
J
TL_DATA
TL_CLK
TL_CLK
vdd18
vdd19
TL_SIG [4]
RL_CLK
RL_DATA
J
K
TATM_DA
TATM_DA
TL_SYNC
RL_CLK
TL_DATA
RL_SYNC
TL_CLK
TL_DATA
K
L
PCH
TATM_DA
TATM_DA
TL_SIG
TL_SYNC
TL_SIG [3]
TL_SIG
RL_CLK
L
M
TATM_DA
TATM_DA
TATM_DA
TATM_CL
TL_DATA
RL_SIG
RL_SYNC
RL_DATA
M
N
Vss13
TL_CLK
RL_SYNC
RL_CLK
vdd20
TL_SYNC
TL_SIG
vss12
N
P
vss15
RL_CLK
vdd21
PCH
RL_SIG [3]
TL_DATA
vss14
P
R
RATM_DA
TL_CLK
RL_CLK
RL_CLK
TL_SIG [2]
TL_SYNC
RL_DATA
RL_SYNC
R
T
TL_CLK
RATM_DA
RATM_DA
RATM_DA
RL_DATA
RL_CLK
TL_DATA
TL_CLK
T
U
RATM_DA
RATM_EN
RATM_DA
RATM_CL
RL_SIG [1]
TL_CLK
RL_SYNC
RL_SIG [2]
U
V
RATM_DA
RATM_DA
TPHY_AD
vdd23
vdd22
RL_CLK
TL_SIG [1]
TL_SYNC
V
W
RATM_SO
TPHY_AD
TPHY_AD
TPHY_AD
PCH
TL_SYNC
RL_SYNC
TL_DATA
W
Y
RATM_CL
RATM_PA
RATM_DA
RATM_DA
RL_SYNC
RL_DATA
TL_CLK
RL_DATA
Y
AA
PCH
RATM_DA
TPHY_AD
RATM_DA
TL_SIG [0]
RL_DATA
RL_SIG
TL_SYNC
AA
AB
RATM_DA
RATM_DA
RATM_DA
A [17]
Bottom View of
352 SBGA Package
(35 mm x 35 mm)
RL_SYNC
TL_DATA
RL_SIG
RL_SYNC
AB
AC
RATM_DA
A [19]
SCAN_MO
vdd4
D [15]
A [15]
D [11]
A [11]
vdd3
D [5]
A [4]
TL_SYNC
TL_SIG
vdd2
RDB
TL_SYNC
RL_SIG
vdd1
CGC_DOU
CGC_SER
CGC_LINE
TRSTB
vdd0
RL_DATA
RL_SIG [0]
LINE_MO
AC
AD
A [18]
vss17
vdd6
A [16]
D [12]
A [12]
D [8]
A [9]
D [6]
A [6]
RL_DATA
RL_DATA
D [1]
A [2]
ALE
ACKB
TL_SIG
TL_DATA
CGC_DOU
NCLK
CGC_LINE
CGC_LINE
RSTB
vdd5
vss16
RL_CLK
AD
AE
vss21
vdd8
vss19
D [13]
A [13]
D [9]
A [10]
D [7]
A [7]
D [3]
RL_SIG
RL_SYNC
D [0]
A [3]
A [0]
CSB
INTB
RL_DATA
TL_SIG
CGC_DOU
TL_CLK_O
CGC_LINE
ADAP_ST
vss20
vdd7
vss18
AE
AF
vss27
vss26
D [14]
A [14]
D [10]
D [2]
A [8]
D [4]
A [5]
PCH
TL_DATA
RL_SIG
vss25
vss24
A [1]
WRB
CGC_DOU
TL_DATA
RL_SYNC
TL_SYNC
PCH
CGC_VALI
CGC_LINE
SRTS_ST
vss23
vss22
AF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1