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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
171
Link Rate Octet
Bit #
7
6
5:4
3:0
T1/E1 Format
ALM
0
ClkRate[1:0]
Phase[3:0]
Table 11 T1/E1 Clock Rate Encoding
ClkRate[1:0]
T1 Clocks / 2KHz
E1 Clocks / 2 KHz
“00” – Nominal
772
1024
“01” – Fast
773
1025
“1x” – Slow
771
1023
When supporting DS3 links, the RL_CLK0/2 and TL_CLK0/2 clocks must be
used directly. In this case the AAL1gator should be configured as an SBI clock
master and the CLK_SOURCE bits in LIN_STR_MODE memory register need to
select the clock pins. That is CLK_SOURCE_RX=’1’ and
CLK_SOURCE_TX=”000”. (Note the remote side on the other side of the SBI
bus will also be using the same external DS3 clock as a master. Therefore both
sides think they are the master and are ignoring the link rate information on the
SBI. Since they are both using the same clock, there will not be a problem since
the buffering of the SBI data is large enough to accommodate jitter caused
directly by the SBI bus).
11.6.3.1.6
Alarms
The SBI specification provides a method for transferring alarm conditions across
the SBI bus. This is optional on a per tributary basis and is valid for T1, E1, DS3
tributaries.
Figure 79 shows the alarm indication bit, ALM, as bit 7 of the Link Rate Octet.
The presence of an alarm condition is indicated by the ALM bit set high in the
Link Rate Octet. The absence of an alarm condition is indicated by the ALM bit
set low in the Link Rate Octet. When SBI_ALRM_EN is set for a given link
associated with a particular tributary and an alarm signal is detected on that
tributary, the SBI_ALRM_DET bit will be set in the EXT_ALRM_REG register for
the link associated with that tributary.
If the SBI_ALRM_INS bit is set in the INS_ALRM_REG register for a given link,
then the ALM bit will be set in the tributary associated with that link.