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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
404
the cell has been read out of the source MCFF FIFO and there are no more cells
to send. Data is placed on RPHY_DATA any cycle following one in which
RPHY_ENB was asserted. In Utopia 1 PHY mode RPHY_ENB can be
deasserted during the cell transfer for data transfer pausing. Figure 96 below
shows the end of transfer behavior in PHY mode. Note that in Utopia 1 mode
the status of RPHY_CLAV should reflect the current cell transfer, thus
RPHY_CLAV remains asserted until the last byte/word of the cell.
Figure 96 UI_SRC_INTF End-of-Transfer (Utopia 1 PHY Mode)
Input must be same value as UI_SRC_ADDR_CFG register
D24
D25
D26
D27
D50
D51
D52
D53
RPHY_CLK(i)
RPHY_ADDR(i)
RPHY_CLAV(o)
RPHY_ENB(i)
RPHY_SOC(o)
RPHY_DATA(o) (16-bit)
RPHY_DATA(o) (8-bit)
In Utopia 2 PHY slave (MPHY) mode, RPHY_ADDR is used for device polling
and selection. RPHY_CLAV is only driven during cycles following ones in which
RPHY_ADDR[4:0] matches the CFG_ADDR[4:0] in the UI_SRC_ADD_CFG
register. When a channel is being polled in Utopia 2 slave mode (MPHY), the
value of RPHY_CLAV will be 1 until the cell has been read out of the FIFO and
there are no more cells to send. In Utopia 2 mode, the SRC_INTF block has to
be selected for data to be driven. This is done when RPHY_ADDR[4:0] matches
source CFG_ADDR[4:0] in the UI_SRC_ADDR_CFG register the cycle before
RPHY_ENB goes low. A start-of-transfer sequence for Utopia 2 PHY slave mode
is shown below in Figure 97. Transfer pausing is supported in Utopia 2 PHY
slave mode, thus RPHY_ENB can be deasserted during the cell transfer and the
data driven by the SRC_INTF will stop one cycle later.