- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363718 > NZ48F4L0QTY (Intel Corp.) StrataFlash Wireless Memory PDF資料下載
參數(shù)資料
| 型號： | NZ48F4L0QTY |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數(shù)： | 71/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | NZ48F4L0QTY |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
71
14.0
Dual-Operation Considerations
The multi-partition architecture of the device allows background programming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
14.1
Memory Partitioning
The L18 flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous
read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at
a time can be in program or erase mode.
The flash device supports read-while-write operations with
bus cycle granularity
and not command
granularity. In other words, it is
not
assumed that both bus cycles of a two cycle command (an erase
command for example) will always occur as back to back bus cycles to the flash device. In
practice, code fetches (reads) may be interspersed between write cycles to the flash device, and
they will likely be directed to a different partition than the one being written. This is especially true
when a processor is executing code from one partition that instructs the processor to program or
erase in another partition.
14.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write
command’s (
Figure 30
, and
Figure 31
). However, a write operation issued between a 2-cycle
commands write sequence causes a command sequence error. (See
Figure 32
)
When reading from the same partition after issuing a Setup command, Status Register data is
returned, regardless of the read mode of the partition prior to issuing the Setup command.
Figure 30.
Operating Mode with Correct Command Sequence Example
Partition A
Partition A
Partition B
0x20
0xD0
0xFF
Address [A]
WE# [W]
OE# [G]
Data [D/Q]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NZ48F4L0QTZ | StrataFlash Wireless Memory |
| NZD560A | NPN Low Saturation Transistor |
| NZF220DFT1G | EMI Filter with ESD Protection |
| NZF220TT1 | EMI Filter with ESD Protection(帶ESD保護(hù)功能的EMI濾波器) |
| NZL5V1AXV3T1 | Zener Voltage Regulators (SC-89 Dual Common Anode Zeners for ESD Protection) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NZ48F4L0QTZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| NZ600N18K | 制造商:n/a 功能描述:Power Module |
| NZ9F10VST5G | 功能描述:穩(wěn)壓二極管 ZENER DIODE RoHS:否 制造商:Vishay Semiconductors 齊納電壓:12 V 電壓容差:5 % 電壓溫度系數(shù):0.075 % / K 齊納電流: 功率耗散:3 W 最大反向漏泄電流:3 uA 最大齊納阻抗:7 Ohms 最大工作溫度:+ 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-214AC 封裝:Reel |
| NZ9F10VT5G | 功能描述:穩(wěn)壓二極管 ZENER DIODE RoHS:否 制造商:Vishay Semiconductors 齊納電壓:12 V 電壓容差:5 % 電壓溫度系數(shù):0.075 % / K 齊納電流: 功率耗散:3 W 最大反向漏泄電流:3 uA 最大齊納阻抗:7 Ohms 最大工作溫度:+ 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-214AC 封裝:Reel |
| NZ9F11VST5G | 功能描述:穩(wěn)壓二極管 ZENER DIODE RoHS:否 制造商:Vishay Semiconductors 齊納電壓:12 V 電壓容差:5 % 電壓溫度系數(shù):0.075 % / K 齊納電流: 功率耗散:3 W 最大反向漏泄電流:3 uA 最大齊納阻抗:7 Ohms 最大工作溫度:+ 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-214AC 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。