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參數(shù)資料
| 型號： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲器） |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
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7
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
Table 2
Command Set Definitions
1
FIRST BUS CYCLE
SECOND BUS CYCLE
SCA LA BLE
OR BASIC
COMMA ND
SET
2
SCS/BCS
SCS/BCS
SCS
SCS/BCS
S
CS/BCS
SCS
SCS/BCS
SCS/BCS
SCS/BCS
BUS
CY CLES
REQ’ D
COMMA ND
OPER
3
A DDR
4
DA TA
5,6
OPER
3
A DDR
4
DA TA
5,6
NOTES
READ ARRAY
READ IDENTIFIER
READ QUERY
READ STATUS REGISTER
CLEAR STATUS REGISTER
WRITE-TO-BUFFER
WORD/BYTE PROGRAM
BLOCK ERASE
BLOCK ERASE, WORD/
BYTE PROGRAM SUSPEND
BLOCK ERASE, WORD/
BYTE PROGRAM RESUME
STS PIN CONFIGURATION
SET BLOCK LOCK BIT
CLEAR BLOCK LOCK BITS
FULL CHIP ERASE
1
2
2
2
1
>2
2
2
1
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
X
X
X
X
X
FFh
90h
98h
70h
50h
E8h
READ
READ
READ
IA
QA
X
ID
QD
SRD
7
BA
X
X
X
WRITE
WRITE
WRITE
BA
PA
BA
N
PD
D0h
8, 9, 10
11, 12
10, 11
11
10h/40h
20h
B0h
SCS/BCS
1
WRITE
X
D0h
11
SCS
SCS
SCS
SCS
2
2
2
2
WRITE
WRITE
WRITE
WRITE
X
X
X
X
B8h
60h
60h
30h
WRITE
WRITE
WRITE
WRITE
X
CC
01h
D0h
D0h
BA
X
X
13
14
10
NOTE:
1. Commands other than those shown above are reserved for future use and should not be used.
2. The SCS is compatible with the Intel
Extended Command Set.
3. Bus operations are defined in Table 1.
4. X = Any valid address within the device
BA = Address within the block being erased or locked
IA = Identifier code address; see Table 11
QA = Query database address
PA = Address of memory location to be programmed
5. ID = Data read from query database
SRD = Data read from status register; see Table 14 for a description of the status register bits
PD = Data to be programmed at location PA; data is latched on the rising edge of WE#
CC = Configuration code; see Table 13
6. The upper byte of the data bus (DQ8–DQ15) during command writes is a “ Don’t Care” in x16 operation.
7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.
See Read Identifier Codes Command section for read identifier code data.
8. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a write buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. (N = 0 is
one byte/word length, and so on.) WRITE-to-BUFFER is a multicycle operation, where a byte/word count of N + 1 is
written to the correct memory address (WA) with the proper data (WD). The CONFIRM command (D0h) is expected after
exactly N + 1 WRITE cycles; any other command at that point in the sequence aborts the buffered WRITE. Writing a
byte/word count outside the buffer boundary causes unexpected results and should be avoided.
10. The WRITE-to-BUFFER , BLOCK ERASE, or FULL CHIP ERASE operation does not begin until a CONFIRM command (D0h) is
issued. Confirm also reactivates suspended operations.
11. If a block is locked (i.e., the block’s lock bit is set to ” 0” ), WP# must be at V
IH
in order to perform BLOCK ERASE,
PROGRAM, and SUSPEND operations. Attempts to issue a BLOCK ERASE, PROGRAM, or SUSPEND operation to a locked
block while WP# is V
IL
will fail.
12. Either 40h or 10h are recognized by the ISM as the byte/word program setup.
13. A block lock bit can be set only while WP# is V
IH
.
14. WP# must be at V
IH
to clear block lock bits. The clear BLOCK LOCK BITS operation simultaneously clears all block lock
bits.
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