參數(shù)資料
型號(hào)： MT28F160S3
廠商： Micron Technology, Inc.
英文描述： 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器)
中文描述： 2梅格× 8 /檢測(cè)起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 3/39頁(yè)
文件大小： 281K
代理商： MT28F160S3
3
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
PIN DESCRIPTIONS
56-PIN TSOP
NUMBERS
55
SY MBOL
WE#
TY PE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Chip Enable: With CE0# or CE1# HIGH, the device is deselected
and power consumption is reduced to standby levels. Both
CE0# and CE1# must be LOW to select the device. All timing
specifications are the same for these two signals.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the ISM to the array read mode, and places the device in
deep power-down mode. All inputs, including CE0#/CE1#, are
“Don’t Care,” and all outputs are High-Z. RP# must be held at
V
IH
during all other modes of operation.
Output Enable: Enables data ouput buffers when LOW. When
OE# is HIGH, the output buffers are disabled.
Write Protect: Controls the lock down function of the flexible
locking feature. When LOW, locked blocks cannot be erased
or programmed, and block lock bits may not be altered.
Address inputs during READ and WRITE operations. A0 is only
used in the x8 mode.
14, 2
CE0#, CE1#
Input
16
RP#
Input
54
OE#
Input
56
WP#
Input
32, 28, 27, 26, 25, 24,
23, 22, 20, 19, 18, 17,
13, 12, 11, 10, 8, 7,
6, 5, 4
31
A0-A20
Input
BYTE#
Input
Byte Enable: When LOW, BYTE# places the device in the x8
mode. When HIGH, BYTE# places the device in the x16 mode
and ignores the A0 input buffer. Address A1 then becomes the
lowest order address.
Programming Voltage: Necessary voltage for erasing blocks,
programming data, or configuring lock bits. Typically, V
PP
is
connected to V
CC
.
Data I/O: Data output pins during any READ operation or data
input pins during a WRITE.
15
V
PP
Input
33, 35, 38, 40, 44, 46, DQ0-DQ15
49, 51, 34, 36, 39, 41,
45, 47, 50, 52
53
Input/
Output
STS
Output
Status: Indicates the status of the ISM. When configured in its
pulse mode, it can pulse to indicate program and/or erase
completion. When configured in level mode (default), it acts
as a RY/BY# pin.
Supply Power: 2.7V–3.6V.
Ground.
No Connect: These pins may be driven or left unconnected.
9, 37, 43
21, 42, 48
1, 3, 29, 30
V
CC
V
SS
NC
Supply
Supply
–
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