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參數(shù)資料
| 型號： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲器） |
| 文件頁數(shù)： | 19/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
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19
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
Table 12
Write Protection Alternatives
OPERA TION
BLOCK
LOCK BIT
0
1
WP#
EFFECT
PROGRAM AND
BLOCK ERASE
V
IL
or V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
Block erase and programming enabled
Block is locked; block erase and programming disabled
Block lock bit override; block erase and programming enabled
All unlocked blocks are erased
Block lock bit override; all blocks are erased
Set or clear block lock bits disabled
Set or clear block lock bits enabled
FULL CHIP ERASE
0,1
X
X
SET OR CLEAR
BLOCK LOCK BITS
Table 13
Configuration Coding Definitions
RESERVED
PULSE ON
WRITE COMPLETE
BIT 1
DQ7–DQ2 are reserved for future use.
PULSE ON
ERASE COMPLETE
BIT 0
BITS 7–2
DQ7–DQ2 = Reserved
DQ1/DQ0 = STS Pin Configuration Codes
00 = Default, RY/BY# level mode
(device ready) indication
01 = Pulse on Erase Complete
10 = Pulse on Flash Program Complete
11 = Pulse on Erase or Program Complete
Default RY/BY# level mode (DQ1/DQ0 = 00)
Used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device’s ISM is busy.
Configuration 01 ER INT, pulse mode
1
Used to generate a system interrupt pulse when
any flash device in an array has completed a
BLOCK ERASE or sequence of queued BLOCK
ERASEs; Helpful for reformatting blocks after file
system free space reclamation or “cleanup.”
Configuration 10 PR INT, pulse mode
1
Used to generate a system interrupt pulse when
any flash device in an array has completed a
PROGRAM operation. Provides highest
performance for servicing continuous BUFFER
WRITE operations.
Configuration ER/PR INT, pulse mode
1
Used to generate system interrupts to trigger the
servicing of flash arrays when either ERASE or
flash PROGRAM operations are completed when a
common interrupt service routine is desired.
Configuration codes 01b, 10b, and 11b are all pulse
modes such that the STS pin pulses low then high
when the operation indicated by the given
configuration is completed.
Configuration command sequences for STS pin
configuration (masking bits DQ7–DQ2 to 00h) are as
follows:
Default RY/BY# level mode:
ER INT (Erase Interrupt):
Pulse on Erase Complete
PR INT (Program Interrupt):
Pulse on Flash Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse on Erase or Program Complete
B8h, 00h
B8h, 01h
B8h, 02h
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250ns.
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