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參數(shù)資料
| 型號(hào)： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器) |
| 中文描述： | 2梅格× 8 /檢測(cè)起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 18/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
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18
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
RY/BY# mode will return to V
OL
. Once a PROGRAM
RESUME command is written, the device automatically
outputs status register data when read. V
PP
must remain
at V
PPH
1/2/3
and V
CC
must remain at V
CC
1/2
while in
program suspend mode. RP# must also remain at V
IH
(the same RP# level used for programming). Refer to
Figure 5 for the PROGRAM SUSPEND/RESUME Flow-
chart.
SET BLOCK LOCK BITS COMMAND
A flexible block locking and unlocking scheme is
enabled via a combination of block lock bits. The block
lock bits gate PROGRAM and ERASE operations. With
WP# = V
IH
, individual block lock bits can be set using the
SET BLOCK LOCK BITS command.
SET BLOCK LOCK BITS is started using a two-cycle
command sequence. The SET BLOCK LOCK BITS setup
along with appropriate block address is written, fol-
lowed by the SET BLOCK LOCK BITS CONFIRM and an
address within the block to be locked. The ISM then
controls the set lock bit algorithm. Once the sequence
is written, the device automatically outputs status
register data when read. The CPU then can detect the
completion of the set lock bit event by analyzing STS in
RY/BY# level mode or status register bit SR7.
Upon completion of the SET BLOCK LOCK BITS
operation, status register bit SR4 should be checked. If
an error is detected, the status register should be cleared.
The CEL will remain in the read status register mode
until a new command is issued.
This two-step sequence of setup followed by execu-
tion ensures that lock bits are not accidentally set. An
invalid SET BLOCK LOCK BITS command will result in
status register bits SR4 and SR5 being set to “1.” Also,
reliable operations occur only when V
CC
= V
CC
1/2
and
V
PP
= V
PPH
1/2/3
. If these voltages are absent, lock bit
contents are protected against alteration. A successful
SET BLOCK LOCK BITS operation requires that WP# =
V
IH
. If it is attempted with WP# = V
IL
, the operation will
fail, and SR1 and SR4 will be set to “1.” See Table 12 for
write protection alternatives and refer to Figure 8 for the
SET BLOCK LOCK BITS Flowchart.
CLEAR BLOCK LOCK BITS COMMAND
The CLEAR BLOCK LOCK BITS command can clear
all set block lock bits in parallel. This command is valid
only when WP# = V
IH
. The CLEAR BLOCK LOCK BITS
operation is started using a two-cycle command se-
quence. A CLEAR BLOCK LOCK BITS SETUP command
is written, followed by a CONFIRM command. Then,
the device automatically outputs status register data
when read (see Figure 10). Once completed, the CPU can
detect the completion of the clear block lock bits event
by analyzing STS in RY/BY# level mode or status register
bit SR7.
This two-step sequence of setup followed by execu-
tion ensures that block lock bits are not accidentally
cleared. An invalid clear block lock bits command
sequence will result in status register bits SR4 and SR5
being set to “1.” Also, a reliable CLEAR BLOCK LOCK
BITS operation can only occur when V
CC
= V
CC
1/2
and
V
PP
= V
PPH
1/2/3
. If a CLEAR BLOCK LOCK BITS operation
is attempted while V
PP
≤
V
PPLK
, SR3 and SR5 will be set
to “1.” If these voltages are absent, the block lock bits
contents are protected against alteration.
When a CLEAR BLOCK LOCK BITS operation is
aborted due to V
PP
or V
CC
transitioning out of valid
range and RP# or WP# active transition, block lock bit
values become undetermined. Then, a repeat of CLEAR
BLOCK LOCK BITS is required to initialize block lock bit
contents to known values.
Once the operation is complete, status register bit
SR5 should be checked. Also, if a clear block lock bits
error is detected, the status register should be cleared.
The CEL will remain in read status register mode until
another command is issued.
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