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參數(shù)資料
| 型號： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲器） |
| 文件頁數(shù)： | 4/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
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2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
OPERATION OVERVIEW
The MT28F10S3 device has an on-chip internal state
machine (ISM) for block erase and programming man-
agement, and lock bit configuration. The device de-
faults to read array mode upon initial device power-up
or return from deep power-down mode. The external
memory control pins allows array read, standby, and
output disable operations. Read array, status register,
query, and identifier codes can be accessed through the
command execution logic (CEL), which is independent
of the V
PP
voltage. Proper programming voltage on V
PP
enables successful block erasure, program, and lock bit
configuration. All block erase, program, and lock bit
configuration functions are accessed via the CEL and
verified through the status register.
Commands are written with standard micro-
processor write timings. The CEL contents become an
input to the ISM that controls the block erase, program-
ming, and lock bit configuration. The ISM regulates the
internal algorithms, including pulse repetition, internal
verification, and data margining. During WRITE cycles,
addresses and data are internally latched. Writing the
appropriate command outputs array data, identifier
codes, or status register data. Interface software that
initiates block erase, programming, and lock bit con-
figuration can be stored in any block. During memory
update, this code is transferred to and executed from
the system RAM. Upon successful completion of an
update, READs are again possible via the READ ARRAY
command. Block erase suspend allows system software
to suspend a block erase to read data from, or program
data to, any other block. Program suspend allows
system software to suspend a program to read data
from any other flash memory location.
DATA PROTECTION
The system designer may choose to make the V
PP
power supply switchable or hardwired to V
PPH
1/2/3
,
depending on the application. Using either configura-
tion will enable designers to optimize the processor-
memory interface.
When V
PP
is lower than V
PPLK
, memory contents are
fixed. When V
PP
is HIGH, the two-step block erase,
program, or lock bit configuration command sequences
provide data protection. When V
CC
voltage is below the
write lockout voltage V
LKO
, or when RP# is at V
IL
, all
WRITE functions are disabled. The device can lock
blocks to provide additional protection from unwanted
code or data changes.
BUS OPERATION
All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
READ
Reading the device is independent of the applied V
PP
voltage and users can obtain block information, query
information, identifier codes, and status register set-
tings. To read, the device must be first placed into the
desired read mode. This can be done by writing the
appropriate read mode command (read array, query,
read identifier codes, or read status register) to the CEL.
The device will automatically reset to read array mode
upon initial device power-up or after exit from deep
power-down mode. Control pins manage the data
flow in and out of the component. CE0#, CE1#, and
OE# must be driven active to obtain data at the outputs.
CE0# and CE1# are the device selection controls, and
when both are active, they enable the selected memory
device. OE# is the data output (DQ0–DQ15) control.
When active, it drives the selected memory data onto
the I/O bus. Both WE# and RP# must be at V
IH
. The
READ Operations timing diagram illustrates a READ
cycle.
OUTPUT DISABLE
When OE# is at a logic HIGH level (V
IH
), the device
outputs are disabled.
STANDBY
When the device is in standby mode and CE0# or
CE1# are at a logic HIGH level (V
IH
), the device power
consumption is substantially reduced. DQ0-DQ15 (or
DQ0-DQ7 in x8 mode) outputs are High-Z, indepen-
dent of OE#. When deselected during block erase,
programming, or lock bit configuration, the device
continues its operation and consumes active power
until operation completion.
DEEP POWER-DOWN
The deep power-down mode occurs when RP# is at
V
IL
. RP# LOW deselects the memory, places output
drivers in High-Z, and turns off all internal circuits. RP#
must be held LOW for time
t
PLPH. A period of
t
PHQV
is required after power-down before initial memory
access outputs are valid. After this wake-up interval,
normal operation is resumed. The CEL resets to read
array mode, and the status register is set to 80h.
RP# LOW will abort the operation during block
erase, programming, or lock bit configuration modes.
STS in RY/BY# mode remains LOW until the RESET
operation is complete. The previously altered memory
contents are no longer valid since the data may be
partially corrupted after programming or partially
altered after an erase or lock bit configuration. A period
of
t
PHWL is required after RP# goes to logic HIGH (V
IH
)
before another command can be written. RP# must be
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