參數(shù)資料
型號(hào)： MT28F160S3
廠商： Micron Technology, Inc.
英文描述： 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器)
中文描述： 2梅格× 8 /檢測(cè)起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 15/39頁(yè)
文件大?。?/td> 281K
代理商： MT28F160S3
15
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
Table 11
Identifier Codes
CODE
Manufacturer
Compatibility Code
Device Code
Block Lock Configuration
Block is unlocked
Block is locked
Reserved for future use
Block Erase Status
Last erase completed
successfully
Last erase did not
complete successfully
Reserved for future use
A DDRESS
1
000000
DA TA
B0
000001
X0002
2
D0
DQ0 = 0
DQ0 = 1
DQ2-DQ7
X0002
2
DQ1 = 0
DQ1 = 1
DQ2-DQ7
READ IDENTIFIER CODES COMMAND
By writing the READ IDENTIFIER CODES com-
mand, the IDENTIFIER CODE operation is initiated.
Following the command write, READ cycles from ad-
dresses shown in Figure 2 (p. 5) retrieve information on
the manufacturer, device, block lock configuration,
and block erase status codes (see Table 11 for identifier
code values). To terminate the operation, write another
valid command. Like the READ ARRAY command, the
READ IDENTIFIER CODES command functions inde-
pendently of the V
PP
voltage. Following the READ
IDENTIFIER CODES command, the information in
Table 11 can be read.
READ STATUS REGISTER COMMAND
The READ STATUS REGISTER command functions
independently of the V
PP
voltage. It is used to determine
the successful completion of programming, block era-
sure, or lock bit configuration. The status register may
be read by writing the READ STATUS REGISTER com-
mand. Once the command is written, all subsequent
READ operations output data from the status register,
with this data being latched on the falling edge of OE#
or CEx#, whichever occurs last. To update the status
register latch, OE# or CEx# must be toggled to V
IH
.
From time
t
WB after a program, block erase, set block
lock bit, or clear block lock bits command sequence,
only SR7 is valid until the ISM completes or suspends
the operation. Device I/O pins DQ0-DQ6 and DQ8-
DQ15 are invalid. Once the operation completes or
suspends (SR7 = 1), all contents of the status register are
valid when read. The extended status register (X SR) may
be read to determine write buffer availability (see Table
15). By writing the WRITE-to-BUFFER command, the
X SR may be read at any time. After writing this com-
mand, all subsequent READ operations output data
from the X SR until another valid command is written.
The contents of the X SR are latched on the falling edge
of OE# or CEx#, whichever occurs last in the READ cycle.
To update the X SR latch, the WRITE-to-BUFFER com-
mand must be re-issued.
CLEAR STATUS REGISTER COMMAND
Status register bits SR5, SR4, SR3, and SR1 are set to
“1s” by the ISM and can only be reset by the CLEAR
STATUS REGISTER command. These bits indicate vari-
ous failure conditions (see Table 14). By allowing system
software to reset these bits, several operations may be
performed. The status register may be polled to deter-
mine if an error occurred during the sequence. To clear
the status register, the CLEAR STATUS REGISTER com-
mand is written. It functions independently of the
applied V
PP
voltage. Note that this command is not
functional during block erase or program suspend
modes.
BLOCK ERASE COMMAND
A BLOCK ERASE is initiated by a two-cycle com-
mand and is executed one block at a time. A BLOCK
ERASE SETUP command is written, followed by a
CONFIRM command. This command sequence re-
quires appropriate sequencing and that an address
within the block be erased. Block preconditioning,
erase, and verify are handled internally by the ISM
(invisible to the system). After the two-cycle block erase
sequence is written, the device automatically outputs
status register data when read (see Figure 6). The CPU
can detect block erase completion by analyzing STS in
RY/BY# level mode or status register bit SR7. Toggle OE#,
CE0#, or CE1# to update the status register.
Upon completion of BLOCK ERASE, status register
bit SR5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CEL
remains in read status register mode until a new com-
mand is issued.
NOTE:
1. A0 should be ignored in this address. The lowest-
order address line is A1 in both word and byte
mode.
2. “ X” selects the specific block lock configuration
code. See Figure 2 for the device identifier code
memory map.
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