參數(shù)資料
型號(hào)： MT28F160S3
廠商： Micron Technology, Inc.
英文描述： 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器)
中文描述： 2梅格× 8 /檢測(cè)起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 17/39頁(yè)
文件大?。?/td> 281K
代理商： MT28F160S3
17
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
mode or status register bit SR7. Upon programming
completion, status register bit SR4 should be checked.
If a programming error is detected, the status register
should be cleared. The ISM verify only detects errors for
“1s” that do not successfully program to “0s.” The CEL
remains in read status register mode until it receives
another command. Refer to Figure 4 for the SINGLE
WORD/BYTE PROGRAM Flowchart. Also, reliable byte/
word programming can only occur when V
CC
= V
CC
1/2
and V
PP
= V
PPH
1/2/3
. In the absence of this high voltage,
contents are protected against programming. If a byte/
word program is tried while V
PP
≤
V
PPLK
, status register
bits SR4 and SR3 will be set to “1.” Successful byte/word
programming requires that the corresponding block
lock bit be cleared. If a byte/word program is attempted
when the corresponding block lock bit is set and WP#
= V
IL
, SR1 and SR4 will be set to “1.”
STS CONFIGURATION COMMAND
Using the STS CONFIGURATION command, the
STS pin can be configured to different states. Once
configured, it remains in that configuration until an-
other CONFIGURATION command is issued or RP# is
LOW. Initially, the STS pin defaults to RY/BY# level
operation. STS LOW indicates that the state machine
is busy, while STS HIGH indicates that the state machine
is ready for a new operation or is suspended.
To change the STS pin to other modes, the STS
CONFIGURATION command must be issued followed
by the desired configuration code. The three alternate
pulse-mode configurations may be used as a system
interrupt as described in Table 13. With these configu-
rations, bit 0 controls erase complete interrupt pulse,
and bit 1 controls write complete interrupt pulse. Once
the device is configured in one of the pulse modes, the
STS pin pulses LOW with a typical pulse width of 250ns.
Issuing the 00h configuration code with the CON-
FIGURATION command resets the STS pin to the
default RY/BY# level mode. Table 13 explains configu-
ration coding definitions. The CONFIGURATION com-
mand may only be given when the device is not busy or
suspended. Check SR7 for device status. An invalid
configuration code will result in status register bits SR4
and SR5 being set to “1.”
BLOCK ERASE SUSPEND COMMAND
This command allows block erase interruption to
read or program data in another block of memory.
Right after starting the block erase process, writing the
BLOCK ERASE SUSPEND command requests that the
ISM suspend the block erase sequence at a predeter-
mined point in the algorithm. When read after the
BLOCK ERASE SUSPEND command is written, the
device outputs the status register. Polling status register
bit SR7 can determine when the BLOCK ERASE opera-
tion has been suspended. When SR7 = 1, SR6 should also
be set to “1,” indicating that the device is in the erase
suspend mode. STS in RY/BY# level mode will also
transition to V
OH
. Specification
t
LES defines the block
erase suspend latency. At this point, a READ ARRAY
command can be written to read data from blocks other
than that which is suspended. A program command
sequence can also be issued during erase suspend to
program data in other blocks. Using the PROGRAM
SUSPEND command (see Program Suspend Command
section), a PROGRAM operation can also be suspended.
During a PROGRAM operation with block erase sus-
pended, status register bit SR7 will return to “0,” and
STS in RY/BY# mode will transition to V
OL
. However,
SR6 will remain “1” to indicate block erase suspend
status.
READ STATUS REGISTER and BLOCK ERASE RE-
SUME are the only other valid commands while block
erase is suspended. Once a BLOCK ERASE RESUME
command is written to the flash memory, the ISM will
continue the block erase process. Status register bits SR6
and SR7 will automatically clear, and STS in RY/BY#
mode will return to V
OL
. Once the ERASE RESUME
command is written, the device automatically outputs
status register data when read (see Figure 8). V
PP
must
remain at V
PPH
1/2/3
and V
CC
must remain at V
CC
1/2
(the
same V
PP
and V
CC
levels used for BLOCK ERASE) while
block erase is suspended. RP#
V
IH
. BLOCK ERASE
cannot resume until program operations initiated
during BLOCK ERASE SUSPEND have completed.
PROGRAM SUSPEND COMMAND
The PROGRAM SUSPEND command enables pro-
gram interruption to read data in other flash memory
locations. After starting the programming process,
writing the PROGRAM SUSPEND command requests
that the ISM suspend the program sequence at a
predetermined point in the algorithm. Once the PRO-
GRAM SUSPEND command is written, the device con-
tinues to output status register data when read. Polling
status register bit SR7 can determine when the program-
ming operation has been suspended. When SR7 = 1, SR2
should also be set to “1” to indicate that the device is
in the program suspend mode. STS in RY/BY# level
mode will also transition to V
OH
. Note that
t
LPS defines
the program suspend latency. A READ ARRAY com-
mand can be written to read data from locations other
than that which is suspended. While programming is
suspended, the only other valid commands are READ
STATUS REGISTER and PROGRAM RESUME. Once a
PROGRAM RESUME command is written, the ISM will
continue the programming process. Then status register
bits SR2 and SR7 will automatically clear and STS in
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