參數(shù)資料
型號(hào)： MT28F160S3
廠商： Micron Technology, Inc.
英文描述： 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器)
中文描述： 2梅格× 8 /檢測(cè)起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 6/39頁(yè)
文件大小： 281K
代理商： MT28F160S3
6
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
Table 1
Bus Operation
MODE
Read
Output Disable
Standby
RP#
V
IH
V
IH
V
IH
CE0#
V
IL
V
IL
V
IL
V
IH
V
IH
X
CE1#
V
IL
V
IL
V
IH
V
IL
V
IH
X
OE#
1
V
IL
V
IH
X
WE
1
V
IH
V
IH
X
A DDRESS
X
X
X
V
PP
X
X
X
DQs
2
D
OUT
High-Z
High-Z
STS
3
X
X
X
NOTES
5, 6
Reset/Power-
Down Mode
Read Identifier
Codes
Read Query
Write
V
IL
X
X
X
X
High-Z
High-Z
4
7
V
IH
V
IL
V
IL
V
IL
V
IH
See
X
D
OUT
High-Z
4
8
Figure 1
See Table 5
X
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
X
D
OUT
D
IN
High-Z
4
X
9
V
PPH
1
V
PPH
2
V
PPH
3
3, 10,
11
NOTE:
1. OE# = V
IL
and WE# = V
IL
concurrently is an undefined state and should not be attempted.
2. DQ refers to DQ0–DQ7 if BYTE# is LOW and DQ0–DQ15 if BYTE# is HIGH.
3. STS in level RY/BY# mode (default) is V
OL
when the ISM is executing internal block erase, programming, or lock bit
configuration algorithms. It is V
OH
when the ISM is not busy, in block erase suspend mode (with programming inactive),
program suspend mode, or deep power-down mode.
4. High-Z will be V
OH
with an external pull-up resistor.
5. Refer to DC Characteristics table. When V
PP
≤
V
PPLK
, memory contents can be read, but not altered.
6. “ X” can be V
IL
or V
IH
for control and address input pins and V
PPLK
or V
PPH
1/2/3
for V
PP
. See the DC Characteristics table
for V
PPLK
and V
PPH
1/2/3
voltages.
7. RP# at GND ± 0.2V ensures the lowest deep power-down current.
8. See Read Identifier Codes Command section for read identifier code data.
9. See Read Query Mode section for read query data.
10. Command writes involving block erase, write, or lock bit configuration are reliably executed when V
PP
= V
PPH
1/2/3
and
V
CC
= V
CC
1/2
(see Write/Erase Current Drain table).
11. Refer to Table 2 for valid D
IN
during a WRITE operation.
WRITE
WRITE commands to the CEL enables reading the
device data, query, identifier codes, and inspection and
clearing of the status register. In addition, when V
PP
=
V
PPH
1/2/3
, block erasure, programming, and lock bit
configuration can also be performed. The BLOCK
ERASE command requires the command and address
within the block to be erased. The BYTE/WORD WRITE
command requires writing the command and address
of the desired location. The CLEAR BLOCK LOCK BITS
command requires the command and an address within
the whole device. SET BLOCK LOCK BITS commands
require the command and address within the block to
be locked.
The CEL is written when CE0#, CE1# (CEx#), and
WE# are active and OE# = V
IH
. The address and data for
a command execution are latched on the rising
edge of WE# or CEx#, whichever goes HIGH first.
Standard microprocessor write timings are used. The
WRITE Operations timing diagram illustrates a WRITE
operation.
COMMAND DEFINITIONS
V
PP
voltage
≤
V
PPLK
allows READ operations from the
status register, identifier codes, or memory blocks.
Placing V
PPH
1/2/3
on V
PP
enables successful BLOCK ERASE,
PROGRAMMING, and LOCK BIT CONFIGURATION
operations. To select device operations, one must write
specific commands into the CEL. Table 2 defines these
commands.
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