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參數(shù)資料
| 型號： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲器） |
| 文件頁數(shù)： | 2/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
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2
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
GENERAL DESCRIPTION (continued)
To achieve optimization of the processor-memory
interface, the device accommodates V
PP
, which is either
switchable during block erase, program, or lock bit
configuration or is hardwired to V
CC
, depending on the
application. V
PP
is treated as an input pin to enable
erasing, programming, and block locking. When V
PP
is
lower than the write lockout voltage, V
LKO
, all program
functions are disabled.
Each block of the device can be independently erased
100,000 times. In addition, program suspend mode
allows system software to suspend programming to
read data from other flash memory locations.
Additionally, the device offers individual block
locking, which is controlled through a combination of
block lock bits. Block erase suspend allows the reading
of data from or the programming of data to any other
block.
The status pin (STS) provides a logic signal output
that acts as an additional indicator of internal state
machine (ISM) activity. This status indicator minimizes
both CPU overhead and system power consumption.
In the default mode, it acts as a RY/BY# pin. When
LOW, STS indicates that the ISM is performing a BLOCK
ERASE, PROGRAM, or LOCK BIT CONFIGURATION.
When HIGH, STS indicates that the ISM is ready for a
new command.
Two chip enable pins (CE#) are used for enabling
and disabling the device to activate the control logic,
input buffer, decoders, and sense amplifiers.
The BYTE# pin allows x8 or x16 READs/WRITEs to
be selected. BYTE# at logic LOW selects an 8-bit mode
using address A0 to select between the low byte and
the high byte. BYTE# at logic HIGH enables 16-bit
operation.
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
Addr.
Buffer/
Latch
Power
(Current)
Control
Addr.
Counter
I/O
Control
Logic
V
PP
Switch/
Pump
Status
Register
Identification
Register
Y -
Decoder
X
State
Machine
A0-A20
OE#
WE#
RP#
V
CC
V
PP
DQ0-DQ15
8
CE0#
8
Output
Buffer
I8
Buffer
Write
Buffer
STS#
64KB Memory Block (0)
64KB Memory Block (1)
64KB Memory Block (2)
64KB Memory Block (31)
64KB Memory Block (29)
64KB Memory Block (30)
8
Query
BYTE#
CE1#
WP#
Command
Execution
Logic
FUNCTIONAL BLOCK DIAGRAM
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