參數(shù)資料
型號(hào)： MT28F160S3
廠商： Micron Technology, Inc.
英文描述： 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲(chǔ)器)
中文描述： 2梅格× 8 /檢測(cè)起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 20/39頁(yè)
文件大小： 281K
代理商： MT28F160S3
20
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
Table 14
Status Register Definition
ISMS
7
ESS
6
ECLBS
5
PSLBS
4
V
PP
S
3
PSS
2
DPS
1
R
0
STATUS REGISTER BIT (SR)
SR7 = INTERNAL STATE MACHINE STATUS (ISMS)
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE suspended
0 = BLOCK ERASE in progress/completed
SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS)
1 = Error in block erasure or clear lock bits
0 = Successful block erase or clear lock bits
SR4 = PROGRAM AND SET LOCK BITS STATUS (PSLBS)
1 = Error in program or block lock bits
0 = Successful program or set block lock bits
SR3 = V
PP
STATUS (V
PP
S)
1 = V
PP
low detect, operation abort
0 = V
PP
OK
DESCRIPTION
Check STS in RY/BY# mode or SR7 to determine
block erase, programming, or lock bit configuration
completion. SR6-SR0 are invalid when SR7 = 0.
If both SR5 and SR4 are “1s” after a block erase
or lock bit configuration attempt, an improper
command sequence was entered.
SR3 does not provide a continuous indication of
V
PP
level. The ISM interrogates and indicates the
V
PP
level only after a BLOCK ERASE, PROGRAM, or
LOCK BIT CONFIGURATION operation. SR3 reports
accurate feedback only when V
PP
= V
PPH
1/2/3
.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = PROGRAM suspended
0 = PROGRAM in progress/completed
SR1 = DEVICE PROTECT STATUS (DPS)
1 = Block lock bit and/or
WP# lock detected, operation abort
0 = Unlock
SR1 does not provide a continuous indication of
block lock bit values. The ISM interrogates the
block lock bit and WP# only after a BLOCK ERASE,
PROGRAM, or LOCK BIT CONFIGURATION operation.
It informs the system, depending on the attempted
operation, if the block lock bit is set.
SR0 is reserved for future use and should be masked
when polling the status register.
SR0 = Reserved for future enhancements
STATUS REGISTER BIT (XSR)
XSR7 = WRITE BUFFER STATUS (WBS)
1 = WRITE-to-BUFFER available
0 = WRITE-to-BUFFER not available
XSR6-0 = Reserved for future enhancements
DESCRIPTION
After a WRITE-to-BUFFER command, XSR7 indicates
that a WRITE-to-BUFFER command is possible.
SR6–SR0 are reserved for future use and should be
masked when polling the status register.
Table 15
Extended Status Register Definition (XSR)
WBS
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
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