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參數(shù)資料
| 型號： | MC68HC08LK60VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA160 |
| 封裝： | 15 X 15 MM, BGA-160 |
| 文件頁數(shù)： | 98/248頁 |
| 文件大?。?/td> | 1727K |
| 代理商： | MC68HC08LK60VF |
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Functional Description
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
Freescale Semiconductor
187
16.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 16.3.4 Pulse-Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the timer channel registers.
An unsynchronized write to the timer channel registers to change a pulse width value could cause
incorrect operation for up to two PWM periods. For example, writing a new value before the counter
reaches the old value but after the counter reaches the new value prevents any compare during that PWM
period. Also, using a timer overflow interrupt routine to write a new, smaller pulse width value may cause
the compare to be missed. The timer may pass the new value before it is written.
Use these methods to synchronize unbuffered changes in the PWM pulse width on channel x:
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
When changing to a longer pulse width, enable channel x timer overflow interrupts and write the
new value in the timer overflow interrupt routine. The timer overflow interrupt occurs at the end of
the current PWM period. Writing a larger value in an output compare interrupt routine (at the end
of the current pulse) could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
16.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The timer channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in timer channel 0 status and control register (TSC0) links channel 0 and channel 1.
The timer channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the timer channel
1 registers enables the timer channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the timer channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and timer
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin if the timer pad is shared with the I/O pad.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the TCH2 pin.
The timer channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in timer channel 2 status and control register (TSC2) links channel 2 and channel 3.
The timer channel 2 registers initially control the pulse width on the TCH2 pin. Writing to the timer channel
3 registers enables the timer channel 3 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the timer channel registers (2 or 3) that control the
pulse width are the ones written to last. TSC2 controls and monitors the buffered PWM function, and timer
channel 3 status and control register (TSC3) is unused.
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