
Timer Interface Module (TIM)
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
184
Freescale Semiconductor
16.3 Functional Description
Figure 16-1 shows the structure of the TIM. The central component of the TIM is the 16-bit timer counter
that can operate as a free-running counter or a modulo up-counter. The timer counter provides the timing
reference for the input capture and output compare functions. The timer counter modulo registers,
TMODH and TMODL, control the modulo value of the timer counter. Software can read the timer counter
value at any time without affecting the counting sequence.
The four TIM channels are programmable independently as input capture or output compare channels.
16.3.1 Timer Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, TCLK. The
prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS2–PS0,
in the timer status and control register select the TIM clock source.
NOTE
This device does not have a TCLK pin.
16.3.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the timer
counter into the timer channel registers, TCHxH and TCHxL. The polarity of the active edge is
programmable. Input capture latency can be up to three bus clock cycles. Input captures can generate
TIM CPU interrupt requests.
NOTE
This device does not have input capture functionality.
$002D
TIM Channel 2 Register High
(TCH2H)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
0000000
0
$002E
TIM Channel 2 Register Low
(TCH2L)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0000000
0
$002F
TIM Channel 3 Status and Control
Register (TSC3)
Read:
CH3F
CH3IE
0
MS3A
ELS3B
ELS3A
TOV3
CH3MAX
Write:
0
Reset:
0000000
0
$0030
TIM Channel 3 Register High
(TCH3H)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
0000000
0
$0031
TIM Channel 3 Register Low
(TCH3L)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0000000
0
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
Figure 16-2. TIM I/O Register Summary (Continued)