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參數(shù)資料
| 型號(hào)： | MC68HC08LK60VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA160 |
| 封裝： | 15 X 15 MM, BGA-160 |
| 文件頁(yè)數(shù)： | 44/248頁(yè) |
| 文件大?。?/td> | 1727K |
| 代理商： | MC68HC08LK60VF |
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Infrared Serial Communications Interface (IrSCI)
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
138
Freescale Semiconductor
SCTIE — SCI transmit interrupt enable bit
This bit enables the SCTE bit to generate SCI transmitter interrupt requests. Setting the SCTIE bit and
clearing the DMA transfer enable bit, DMATE, in SCC3 enables the SCTE bit to generate CPU
interrupt requests.
1 = SCTE enabled to generate CPU interrupt if DMATE is cleared
0 = SCTE not enabled to generate interrupt requests
TCIE — Transmission complete interrupt enable bit
This bit enables the TC bit to generate SCI transmitter CPU interrupt requests.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI receive interrupt enable bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests or SCI
receiver DMA service requests. Setting the SCRIE bit and clearing the DMA receive enable bit,
DMARE, in SCC3 enables the SCRF bit to generate CPU interrupt requests.
1 = SCRF enabled to generate interrupt requests if DMATE is cleared
0 = SCRF not enabled to generate interrupt requests
ILIE — Idle line interrupt enable bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter enable bit
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the high impedence state. Clearing and then setting
TE during a transmission queues an idle character to be sent after the character currently being
transmitted.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RE — Receiver enable bit
Setting this bit enables the receiver. Clearing the RE bit disables the receiver but does not affect
receiver interrupt flag bits.
1 = Receiver enabled
0 = Receiver disabled
NOTE
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver wakeup bit
This bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE
bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby
state and clears the RWU bit.
1 = Standby state
0 = Normal operation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68HC08LN56 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
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| MC68HC08MR4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:In-Circuit Simulator |
| MC68HC08P4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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