
SIM Counter
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
Freescale Semiconductor
65
6.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the
LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles
later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
NOTE
The MC68HC(9)08LK60 does not have an LVI module.
6.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the
clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of
CGMXCLK.
6.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
6.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of
4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode. External crystal applications should use
the full stop recovery time, that is, with SSREC cleared.
NOTE
The MC68HC(9)08LK60 does not allow stop mode operation.
6.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter.
(See 6.6.2 Stop Mode for details.) The SIM counter is
internal reset recovery sequences.)
6.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
Interrupts:
–
Maskable hardware CPU interrupts
–
Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts