- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67966 > MC68HC08LK60VF (FREESCALE SEMICONDUCTOR INC) 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA160 PDF資料下載
參數(shù)資料
| 型號： | MC68HC08LK60VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA160 |
| 封裝： | 15 X 15 MM, BGA-160 |
| 文件頁數(shù)： | 225/248頁 |
| 文件大?。?/td> | 1727K |
| 代理商： | MC68HC08LK60VF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁當前第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁
Clock Generator Module (CGMB)
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
78
Freescale Semiconductor
loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on
the width and direction of the correction pulse. The filter can make fast or slow corrections depending on
its mode, described in 7.3.2.2 Acquisition and Tracking Modes. The value of the external capacitor and
the reference frequency determines the speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final
reference frequency fRDV. The circuit determines the mode of the PLL and the lock condition based on
this comparison.
7.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See 7.5.2 PLL Bandwidth Control Register.)
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See 7.3.3 Base Clock Selector Circuit.) The PLL is in tracking mode
automatically when not in acquisition mode or when the ACQ bit is set.
7.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 7.5.2 PLL
Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. (See 7.3.3 Base Clock Selector Circuit.) If
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See 7.6
Interrupts for information and precautions on using interrupts.) These conditions apply when the PLL is in
automatic bandwidth control mode:
The ACQ bit (see 7.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the
The ACQ bit is set when the VCO frequency is within a certain tolerance,
TRK, and is cleared when
the VCO frequency is out of a certain tolerance,
Specifications for more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance,
LOCK, and is cleared
when the VCO frequency is out of a certain tolerance,
Specifications for more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See 7.5.1 PLL Control Register.)
相關PDF資料 |
PDF描述 |
|---|---|
| MCCF68HC08LK60 | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC150 |
| MC68HC08LT8CFGE | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC11G5CFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11G5CFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| MC68HC11L6VFU23 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC08LN56 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC08LT8 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC08LT8CFGE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC08MR4 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:In-Circuit Simulator |
| MC68HC08P4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
發(fā)布緊急采購，3分鐘左右您將得到回復。