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參數(shù)資料
| 型號(hào)： | MC68HC08LK60VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA160 |
| 封裝： | 15 X 15 MM, BGA-160 |
| 文件頁(yè)數(shù)： | 229/248頁(yè) |
| 文件大小： | 1727K |
| 代理商： | MC68HC08LK60VF |
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Functional Description
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
Freescale Semiconductor
81
Refer to Table 7-1 for a numeric example with numbers in hexadecimal notation.
NOTE
The numeric examples given in Table 7-1 assume a crystal frequency
of 38.4 kHz.
7.3.2.5 Special Programming Exceptions
The programming method described in 7.3.2.4 Programming the PLL does not account for three possible
exceptions. A value of 0 for R, N, or L is meaningless when used in the equations given. To account for
these exceptions:
A 0 value for R or N is interpreted exactly the same as a value of one at the minimum frequency
and the VCO range power-of-two bits.
A 0 value for L disables the PLL and prevents its selection as the source for the base clock. (See
7.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base
clock.
Table 7-1. Numeric Example of PLL Register Programming
Bus frequency
E
P
N
L
R
307,200 Hz
1
10
1
614,400 Hz
1
20
1
652,800 Hz
2
11
1
691,200 Hz
2
12
1
729,600 Hz
2
13
1
768,000 Hz
2
14
1
806,400 Hz
2
15
1
998,400 Hz
2
1a
1
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