
Serial Peripheral Interface Module (SPI)
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
148
Freescale Semiconductor
13.3 Functional Description
shows the structure of the SPI module.
The SPI module allows full-duplex, synchronous, serial communication among the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
The following paragraphs describe the operation of the SPI module.
13.3.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$000D
SPI Control Register
(SPCR)
Read:
SPRIE
DMAS
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
Write:
Reset:
00
1
0
10
00
$000E
SPI Status and Control Register
(SPSCR)
Read:
SPRF
ERRIE
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
Write:
Reset:
00
0
10
00
$000F
SPI Data Register
(SPDR)
Read:
R7R6
R5
R4R3R2R1R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Indeterminate after reset
= Unimplemented
Figure 13-1. SPI I/O Register Summary