
I/O Registers
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
Freescale Semiconductor
191
TOF — Timer overflow flag bit
This read/write flag is set when the timer counter reaches the modulo value programmed in the timer
counter modulo registers. Clear TOF by reading the timer status and control register when TOF is set
and then writing a logic 0 to TOF. If another timer overflow occurs before the clearing sequence is
complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = Timer counter has reached modulo value.
0 = Timer counter has not reached modulo value.
TOIE — Timer overflow interrupt enable bit
This read/write bit enables timer overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
TSTOP — Timer stop bit
This read/write bit stops the timer counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the timer counter until software clears the TSTOP bit.
1 = Timer counter stopped
0 = Timer counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — Timer reset bit
Setting this write-only bit resets the timer counter and the timer prescaler. Setting TRST has no effect
on any other registers. Counting resumes from $0000. TRST is cleared automatically after the timer
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and timer counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the timer counter
at a value of $0000.
PS[2:0] — Prescaler select bits
These read/write bits select either the PTE3/TCLK pin or one of the seven prescaler outputs as the
input to the timer counter as
NOTE
TCLK is a floating input pin. Do not select PS2–PS0 = 111.
Address:
$0020
Bit 7
654321
Bit 0
Read:
TOF
TOIE
TSTOP
00
PS2
PS1
PS0
Write:
0
TRST
Reset:
00000000
= Unimplemented
Figure 16-4. Timer Status and Control Register (TSC)