
FLASH Memory
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
42
Freescale Semiconductor
4.7 FLASH2 Block Protect Register
The block protect register is implemented as an I/O register. Each bit, when programmed, protects a
range of addresses in the FLASH.
BPR3 — Block protect register bit 3
This bit protects the upper half portion of full-size 32-K array. Since FLASH2 is 28 Kbytes, the block
protect address range is $4000–$7FFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block protect register bit 2
This bit protects the upper 3/4 portion of full-size 32-K array. Since FLASH2 is 28 Kbytes, the block
protect address range is $2000–$7FFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block protect register bit 1
This bit protects the upper 7/8 portion of a full size 32-K array. Since FLASH2 is 28 Kbytes, the block
protect address range is $1000–$7FFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR0 — Block protect register bit 0
This bit protects all the memory contents in the address range $1000–$7FFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
By programming the block protect bits, a portion of the memory will be locked so that no further erase or
program operations may be performed. Programming more than one bit at a time is redundant. If both
BPR3 and BPR2 are set, for instance, the address range $2000–$7FFF is locked. If all bits are cleared,
then all of the memory is available for erase and program.
4.8 Block Protection
Because of the ability of the on-board charge pump to erase and program the FLASH memory in the
target application, provision is made for protecting blocks of memory from unintentional erase or program
operations. This protection is done by reserving a location in the I/O space for block protect information.
If the address range for an erase or program operation includes a protected block, the PGM or ERASE
bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high
voltage is allowed in the array.
Address:
$0032
Bit 7
654321
Bit 0
Read:
Write:
BPR3
BPR2
BPR1
BPR0
Reset:
XXXX
1111
= Unimplemented
X = Indeterminate
Figure 4-5. FLASH2 Block Protect Register (FL2BPR)