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參數(shù)資料
| 型號(hào)： | MC68HC08LK60VF |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PBGA160 |
| 封裝： | 15 X 15 MM, BGA-160 |
| 文件頁(yè)數(shù)： | 247/248頁(yè) |
| 文件大?。?/td> | 1727K |
| 代理商： | MC68HC08LK60VF |
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Functional Controller Module (FCM)
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
98
Freescale Semiconductor
cleared using the CHRC bit in the timebase control register. See Figure 8-4. The timebase counter can
also be cleared by setting the TBCLR in the timebase control register. See Figure 8-4.
NOTE
This section assumes that a 32.000-kHz oscillator or a 38.400-kHz
oscillator is used, according to the software option selected. These crystals
will generate precise interrupts. Crystals of a frequency two times these
frequencies can also be used to generate accurate RTC clock control. Any
other oscillator frequency will not provide accurate 100 Hz and 1 Hz
counters.
8.4.3 COP Watchdog Timer Submodule
The computer operating properly (COP) or watchdog timer subsystem is a software selectable feature
which will generate a system reset if not serviced within the specified watchdog timeout period. The
watchdog timer counter chain is derived from an output of the timebase circuit. This input signal is divided
to give the watchdog timer reset rate selected by the first write to the COP select bits in the timebase
control register.
A watchdog timer reset is performed by writing any data to address $FFFF. This will reset the counter
chain and begin the timeout countdown again. The watchdog timer counter chain is also cleared when
the MCU is in reset.
The value of the two watchdog timer rate select bits in the timebase control register (TBCR) determines
the watchdog timer timeout rate. These bits can be written only on the first write to this register after a
reset. If these bits are never written to, the watchdog timer reset rate will be set at 1 second when a 32-kHz
crystal is used (see Table 8-1).
NOTE
Although these bits default to 0, the user should write to these bits to
prevent subsequent writes from changing the timeout rate. A bit set/clear
for any bit in this register is executed as a read-modify-write of this register.
If used as the first write to this register, further writes to CRS[1:0] would not
be valid, and the default value would still be set.
The CPU clock halts during wait mode, but the oscillator and the watchdog timer system are still active.
The software should exit wait mode to service the watchdog timer system before the COP timeout period.
If the STOP instruction is executed on an MCU with stop mode enabled, the watchdog timer circuit will be
disabled. The COP timer is enabled when the MCU comes out of reset.
NOTE
The MC68HC(9)08LK60 does not allow stop mode operation.
8.5 Interrupts
The RTC submodule is capable of generating interrupts. Three different interrupts can be generated by
the clock sections of the real-time clock submodule:
1 minute, 1 Hz, 2 Hz, or 4 Hz
Alarm
Chronograph, 10 Hz
These interrupts are enabled by setting the corresponding bit in the RTC control register.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC08LN56 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:General Release Specification |
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| MC68HC08P4 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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