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參數(shù)資料
| 型號： | MB90242A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 32 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, SQFP-80 |
| 文件頁數(shù)： | 94/258頁 |
| 文件大小： | 2010K |
| 代理商： | MB90242A |
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3.5 Power Saving Modes
178
Chapter 3: Operation
s Wake-up from Sleep Mode
Sleep mode can be exited by input of a reset signal or occurrence of an interrupt.
If a reset is used to release sleep mode, the MB90242A will apply a reset upon wake-up from sleep
mode.
Sleep mode will also be released when an interrupt of level 7 or higher (priority level) is generated by
an internal resource circuit. After release, the same processing is applied as for a normal interrupt. If the
interrupt is accepted according to the set values of the I flag, ILM bit and interrupt control register
(ICR), the CPU will execute the next command following the STBYC write instruction (as long as it
does not hold an interrupt) and then will execute the interrupt processing after that instruction. If the
interrupt is not accepted, execution will continue with the next instruction following the command that
caused the transition to sleep mode.
(3) Stop Mode
s Transition to Stop Mode
Transition to stop mode is initiated by writing '1' to the STP bit in the standby control register
(STBYC).
In stop mode, the source oscillation is stopped, stopping all MB90242A device functions. This is
therefore the mode with the lowest power mode in which data is retained.
Also, the SPL bit in the STBYC register can be used to determine whether external pins are placed in
high-impedance state or retain their values at the state immediately preceding the transition to stop
mode.
If an interrupt request is generated at the time that '1' is written to the STP bit, transition to stop mode
will not occur. In this case if the CPU status does not accept the interrupt, it will execute the next
instruction. If the CPU status does accept the interrupt, it will execute the next command following the
STBYC write instruction (as long as it does not hold an interrupt), and then branch to the interrupt
processing program after the completion of the next instruction.
In sleep mode, the dedicated registers (such as accumulators) and contents of internal RAM are
retained.
s Wake-up from Stop Mode
Stop mode can be exited by input of a reset signal or occurrence of an interrupt.
If a reset is used to exit stop mode, the MB90242A will apply a reset upon wake-up from stop mode.
After wake-up from stop mode, the standby control circuit will move first to oscillation stabilization
wait mode before releasing the stop mode control. Also, a reset factor is used for wake-up from stop
mode, the reset sequence applies an oscillation stabilization wait period before reset.
During stop mode, an interrupt of level 7 or higher (priority level) can be generated using an external
interrupt signal to release the MB90242A from stop mode. The wake-up sequence first passes through
an oscillation stabilization period defined by the OSC1, OSC0 bits, then follows the normal interrupt
processing sequence according to the values of the I flag, ILM bit and interrupt control register (ICR),
and the CPU will execute the next instruction following the STBYC write instruction (as long as it does
not hold an interrupt) and then will execute the interrupt processing after the completion of the next
program. If the interrupt is not accepted, execution will continue with the next instruction following the
command that caused the transition to spot mode.
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