2.1 CPU
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Chapter 2:
Hardware Configuration
2.1 CPU
The F2MC-16F CPU core is a high-performance 16-bit CPU designed for applications requiring high-
speed, real-time processing such as industrial applications, office automation (OA) products, and automo-
tive devices. The F2MC-16F instruction set is designed to be optimized for controller applications, and can
handle a wide variety of control functions with high speed and high efficiency. In addition, while the
F2MC-16F core is designed as a 16-bit data processing CPU, an on-chip 32-bit accumulator is included for
handling of 32-bit data. This enables a number of instructions to include 32-bit data processing capability.
Memory space can be expanded to a maximum of 16 Mbytes, and can be accessed by either the linear
pointer or bank access method. The instruction set, based on F2MC-16 architecture, has been enhanced
with additional instructions for high level languages, expanded addressing mode and additional coded mul-
tiplication and division instructions. The F2MC-16F is upwardly compatible with F2MC-16 CPUs at object
code level.
The principal features of the F2MC-16F CPU are:
Minimum instruction execution time .................... 62.5 ns (at 32 MHz source oscillation)
Memory space ....................................................... 16MB: supports both linear and bank access
Instruction set optimized for controller applications
Wide variety of data types .................................... bit / byte / word / long word
Expanded addressing mode................................... 25 modes
High coding efficiency
32-bit accumulator for higher computational accuracy (32-bit length)
Strengthened multiplication/division instructions (coded computation instructions added)
Powerful interrupt functions
Priority levels ...................................................... 8 levels (programmable)
CPU-independent automatic transfer
Expanded intelligent I/O service
.......................... Expanded and accelerated access area
.......................... Maximum 15 channels
Instruction set adapted for high level language (C) and multitasking
System stack pointer
Wide variety of pointers
High-symmetry instruction set
Barrel shift instructions
Stack check function
Improved execution speed
.......................... Instruction operations revised for higher speed
.......................... 8-byte queuing