
2.1 CPU
44
Chapter 2: Hardware Configuration
Fig. 2.1.26 Flow of Interrupt Operations
I:
CCR register flag
ILM:
CPU interrupt level mask register
IY:
Internal resource interrupt request flag
IE:
Internal resource interrupt enable flag
ISE:
EI2OS enable flag
IL:
Interrupt resource interrupt request level
S:
CCR register flag
Fetch and decode next instruction
Execute normal processing
Update PC register
Hardware interrupt
ISE = 1
Save contents of PS, PC, PCB,
DTB, ADB, DPR, A registers to
SSP stack, then set ILM=IL
Expanded intelligent I/
O service processing
I & IY & IE = 1
AND
ILM > IL
INT instruction?
End of string
instruction
repetition?
Software interrupt
Save contents of PS, PC, PCB,
DTB, ADB, DPR, A registers to
SSP stack, then set I=0
Set S
←1, fetch interrupt vector,
update PCB and PC registers
YES
NO
YES
NO