
2.1 CPU
32
Chapter 2: Hardware Configuration
Processor Status Register (PS)
The PS register is configured from bits that perform CPU operating controls and bits that indicate CPU
status. As shown in Figure 2.1.15, The upper byte of the PS register is composed of the register bank
pointer (RP) which indicates the starting address of the register bank, and the interrupt level mask reg-
ister (ILM), and the lower byte of PS consists of the condition code register (CCR) which contains flags
set to '1' or '0' depending on results of instruction execution and interrupt generation.
Fig. 2.1.15 PS Register Configuration
(1) Condition Code Register (CCR)
Figure 2.1.16 shows the configuration of the condition code register, and Table 2.1.3 describes its func-
tions.
Fig. 2.1.16 Condition Code Register Configuration
Table 2.1.3 Flag Functions
Flag name
Function
I
Interrupt enable flag
The I flag is set to '1' to enable all interrupt requests other than software
interrupts. When the flag is '0' interrupts are masked. The reset value is '0.'
S
Stack flag
The S flag is set to '0' to select the USP register as the pointer used for
stack operations. When the flag is '1' the SSP register is selected. Follow-
ing an interrupt or reset, the value is reset to '1.'
T
Sticky bit flag
The T flag is set to '1' when one or more "1s" are contained in the data
shifted out from the carry field during execution of logical right-shift or
arithmetic right-shift instructions. The value is '0' at all other times. When
the shift value is zero places, the bit is set to '0.'
N
Negative flag
This flag is set to '1' if the MSB of the results of arithmetic calculation is
'1' and '0' when the MSB is '0.'
Z
Zero flag
The Z flag is set to '1' when the results of arithmetic calculation are all
zeros, and is set to '0' at all other times.
V
Overflow flag
The V flag is set to '1' when execution of an arithmetic calculation results
in a coded value indicating an overflow, and is set to '0' at all other times.
C
Carry flag
The C flag is set to '1' when an arithmetic calculation requires the MSB to
be carried up or down one or more places, and is set to '0' at all other times.
PS
ILM
RP
CCR
15
13 12
8 7
0
–
I
ST
N
Z
VC
76543210
:CCR