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| 型號(hào)： | MB90242A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 32 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, SQFP-80 |
| 文件頁(yè)數(shù)： | 201/258頁(yè) |
| 文件大?。?/td> | 2010K |
| 代理商： | MB90242A |
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2.1 CPU
42
Chapter 2: Hardware Configuration
Table 2.1.12 Interrupt Numbers and Interrupt Vectors Assigned
(3) Operation
Each internal resource with a hardware interrupt function has both an 'interrupt request flag' that indi-
cates whether an interrupt request has been made or not, and an 'interrupt enable flag' used to select
whether that circuit will send its interrupt signal to the CPU or not. Each interrupt request flag is set by
the occurrence of a particular event within that internal resource, and if the interrupt enable flag has an
'enable' setting, the resulting interrupt request will then be output from the internal resource to the inter-
rupt controller.
The interrupt controller compares individual interrupts simultaneously received with the interrupt lev-
els (IL) in the interrupt control register (ICR), selects the highest-level interrupt (the one with the low-
est IL value) and notifies the CPU. If more than one interrupt with the same level is received, the lowest
interrupt number is given priority. For the relation between interrupt requests and ICR values, see sec-
tion 2.2.3 "Interrupt Level Assignments."
The CPU receives the interrupt, compares its level with the ILM field in the processor status (PS) regis-
ter, and if the value of the interrupt level is less than the ILM setting and the I flag in the PS register has
the value '1,' microcoding for interrupt processing will begin as soon as the currently executing instruc-
tion is ended.
The top of the interrupt processing microcode references the ISE bit in the interrupt controller's ICR
register, verifies that the value of that bit is '0' (0=interrupt), and then starts the main sequence of the
interrupt processing routine.
In interrupt processing, the 12 bytes in the A, DPR, ADB, DTB, PCB, PC and PS registers are saved to
the area of memory designated by the SSB and SSP registers, the contents of the 3-byte interrupt vector
is read and loaded into the PC and PCB register, the contents of the ILM field in the PS register are
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
Hardware interrupt
INT 0
FFFFFCH
FFFFFDH
FFFFFEH
Not used
#0
None
…
INT 7
FFFFE0H
FFFFE1H
FFFFE2H
Not used
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDF
#8
(RESET vector)
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
None
INT 10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception>
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
Hardware interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Not used
#12
Hardware interrupt #1
INT 13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
Hardware interrupt #2
INT 14
FFFFC4H
FFFFC5H
FFFFC6H
Not used
#14
Hardware interrupt #3
…
INT 254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
Open
INT 255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
<Stack fault>
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