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| 型號(hào)： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁(yè)數(shù)： | 87/138頁(yè) |
| 文件大小： | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
52
MC68HC16Y1TS/D
3.6.2 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in an inactive, high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy-
cles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the reset input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-
impedance state for 10 cycles, then it is tested again. The process repeats until RESET is released.
3.6.3 Power-On Reset
When the SCIM clock synthesizer is used to generate system clocks, power-on reset involves special
circumstances related to application of system and clock synthesizer power. Regardless of clock
source, voltage must be applied to clock synthesizer power input pin VDDSYN, so that the MCU can op-
Table 17 Module Pin Functions
Module
Pin Mnemonic
Function
ADC
PADA[7:0]/AN[7:0]
DISCRETE INPUT
VRH
REFERENCE VOLTAGE
VRL
REFERENCE VOLTAGE
CPU
DSI/IPIPE1
DSO/IPIPE0
BKPT/DSCLK
GPT
PGP7/IC4/OC5
DISCRETE INPUT
PGP[6:3]/OC[4:1]
DISCRETE INPUT
PGP[2:0]/IC[3:1]
DISCRETE INPUT
PAI
DISCRETE INPUT
PCLK
DISCRETE INPUT
PWMA, PWMB
DISCRETE OUTPUT
MCCI
PMC7/TXDA
DISCRETE INPUT
PMC6/RXDA
DISCRETE INPUT
PMC5/TXDB
DISCRETE INPUT
PMC4/RXDB
DISCRETE INPUT
PMC3/SS
DISCRETE INPUT
PMC2/SCK
DISCRETE INPUT
PMC1/MOSI
DISCRETE INPUT
PMC0/MISO
DISCRETE INPUT
TPU
TP[15:0]
TPU INPUT
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