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參數(shù)資料
| 型號： | M68HC16Y1CFC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 24/138頁 |
| 文件大?。?/td> | 784K |
| 代理商： | M68HC16Y1CFC |
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MOTOROLA
MC68HC16Y1
12
MC68HC16Y1TS/D
2.5 Data Types
The CPU16 supports the following data types:
— Bit data
— 8-bit (byte) and 16-bit (word) integers
— 32-bit long integers
— 16-bit and 32-bit signed fractions (MAC operations only)
— 20-bit effective address consisting of 16-bit page address plus 4-bit extension
A byte is 8 bits wide and can be accessed at any byte location. A word is composed of two consecutive
bytes, and is addressed at the lower byte. Instruction fetches are always accessed on word boundaries.
Word operands are normally accessed on word boundaries as well, but may be accessed on odd byte
boundaries, with a substantial performance penalty.
To be compatible with the M68HC11, misaligned word transfers and misaligned stack accesses are al-
lowed. Transferring a misaligned word requires two successive byte operations.
2.6 Addressing Modes
The CPU16 provides 10 types of addressing. Each type encompasses one or more addressing modes.
Six CPU16 addressing types are identical to M68HC11 addressing types.
All modes generate ADDR[15:0]. This address is combined with ADDR[19:16] from an extension field
to form a 20-bit effective address. Extension fields are part of a bank switching scheme that provides
the CPU16 with a 1 Mbyte address space. Bank switching is transparent to most instructions — AD-
DR[19:16] of the effective address change when an access crosses a bank boundary. However, it is
important to note that the value of the associated extension field is dependent on the type of instruction,
and generally does not change when this occurs.
In the immediate modes, the instruction argument is contained in bytes or words immediately following
the instruction. The effective address is the address of the byte following the instruction. The AIS, AIX/
Y/Z, ADDD and ADDE instructions have an extended 8-bit mode where the immediate value is an 8-bit
signed number that is sign-extended to 16 bits, then added to the appropriate register — this decreases
execution time.
Extended mode instructions contain ADDR[15:0] in the word following the opcode. The effective ad-
dress is formed by concatenating EK and the 16-bit extension.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension fields, are used
to calculate the effective address. Signed 16-bit mode and signed 20-bit mode are extensions to the
M68HC11 indexed addressing mode.
For 8-bit indexed mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in the index register and its associated extension field.
For 16-bit mode, a 16-bit signed offset contained in the instruction is added to the value contained
in the index register and its associated extension field.
For 20-bit mode, a 20-bit signed offset is added to the value contained in the index register. This
mode is used for JMP and JSR instructions.
Inherent mode instructions use information available to the processor to determine the effective ad-
dress. Operands (if any) are system resources and are thus not fetched from memory.
Accumulator offset mode adds the contents of 16-bit accumulator E to one of the index registers and its
associated extension field to form the effective address. This mode allows use of index registers and
an accumulator within loops without corrupting accumulator D.
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